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NANO-CHIPS 2030 pp 47–88Cite as

The Future of Ultra-Low Power SOTB CMOS Technology and Applications

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Abstract

Ultra-low power technology has drawn much attention recently as the number of connecting (Internet-of-Things) devices rapidly increases. The silicon-on-thin-buried oxide (SOTB) technology is a CMOS device technology that uses fully depleted silicon-on-insulator (FDSOI) transistors with a thin buried oxide layer enabling enhanced back-bias controllability and that can be monolithically integrated with the conventional bulk CMOS circuits. It can significantly reduce both the operation and the standby powers by taking advantage of low-voltage operation and back-biasing, respectively. In this chapter, advantages of the SOTB technology in terms of ultra-low power, circuits design and chip implementation examples including ultra-low power micro-controllers operating with harvested power, reconfigurable logic circuits, analog circuits, are reviewed, and a future perspective is shown.

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Notes

  1. 1.

    The term “Internet of Things” was firstly used by Kevin Ashton in 1999 [1], while the term has become widely known in the early 2010s.

  2. 2.

    In the general system with a series regulator connected to a power source, the power due to the difference between supply and operating voltages is consumed in the series regulator, and thus the total power consumption is proportional to the current consumption. On the other hand, in the system with a power management using a dc-dc converter, the battery life is determined by the average power consumption of the system.

  3. 3.

    γ is defined as ∂Vth/∂Vbb. at around Vbb = 0.

  4. 4.

    In quantum computing, the key index of progress is not the size, voltage, nor clock frequency. The quantum decoherence can be the alternative [92].

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Acknowledgements

The part of the work, especially on developing the SOTB technology by the Low-power Electronics Association and Project (LEAP), is supported by the Ministry of Economy, Trade and Industry (METI) and the New Energy and Industrial Technology Development Organization (NEDO). Part of the chip fabrication by the universities is done under a support of VLSI Design and Education Center (VDEC) in collaboration with Renesas Electronics Corporation, Cadence Corporation, Synopsys Corporation and Mentor Graphics Corporation.

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Authors and Affiliations

  1. Hitachi, Ltd., Tokyo, Japan

    Nobuyuki Sugii

  2. Renesas Electronics Corp., Tokyo, Japan

    Shiro Kamohara

  3. The University of Tokyo, Tokyo, Japan

    Makoto Ikeda

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  1. Nobuyuki Sugii
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  2. Shiro Kamohara
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  3. Makoto Ikeda
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Correspondence to Nobuyuki Sugii .

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  1. Department of Electrical Engineering, Stanford University, Stanford, CA, USA

    Boris Murmann

  2. Sindelfingen, Baden-Württemberg, Germany

    Bernd Hoefflinger

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Sugii, N., Kamohara, S., Ikeda, M. (2020). The Future of Ultra-Low Power SOTB CMOS Technology and Applications. In: Murmann, B., Hoefflinger, B. (eds) NANO-CHIPS 2030. The Frontiers Collection. Springer, Cham. https://doi.org/10.1007/978-3-030-18338-7_6

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