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NANO-CHIPS 2030 pp 227–246Cite as

Coarse-Grained Reconfigurable Architectures

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Abstract

Current trends in technology scaling, coupled with the increasing compute demands with a limited power budget, has spurred research into specialized accelerator architectures. Coarse-Grained Reconfigurable Architectures (CGRAs) have been shown to achieve higher performance and energy efficiency compared to conventional instruction-based architectures by avoiding instruction overheads with reconfigurable data and control paths. CGRAs also avoid the hardware and programming overheads of fine-grained alternatives such as Field-Programmable Gate Arrays (FPGAs) by raising the hardware abstraction. Designing efficient CGRAs requires a careful calibration of the granularity of its elements and building automated compilation flow to map high-level programs to the reconfigurable elements. This chapter reviews the challenges and opportunities in the field of CGRAs.

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References

  1. Y. Chen, T. Luo, S. Liu, S. Zhang, L. He, J. Wang, L. Li, T. Chen, Z. Xu, N. Sun, O. Temam, Dadiannao: a machine-learning supercomputer, in 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture (Dec 2014), pp. 609–622

    Google Scholar 

  2. L. Wu, A. Lottarini, T.K. Paine, M.A. Kim, K.A. Ross, Q100: the architecture and design of a database processing unit, in Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS ’14, New York, NY, USA. (ACM, 2014), pp. 255–268

    Google Scholar 

  3. Y. Chen, T. Krishna, J. Emer, V. Sze, Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks, in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (IEEE, 2016), pp. 262–263

    Google Scholar 

  4. S. Han, X. Liu, H. Mao, J. Pu, A. Pedram, M.A. Horowitz, W.J. Dally, Eie: efficient inference engine on compressed deep neural network. arXiv preprint arXiv:1602.01528 (2016)

  5. J. Dean, D. Patterson, C. Young, A new golden age in computer architecture: empowering the machine-learning revolution. IEEE Micro 38(2), 21–29 (2018)

    Article  Google Scholar 

  6. K. Olukotun, Designing computer systems for software 2.0, isca 2018 keynote. http://iscaconf.org/isca2018/docs/Kunle-ISCA-Keynote-2018.pdf (2018)

  7. M. Horowitz, 1.1 Computing’s energy problem (and what we can do about it), in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (Feb 2014), pp. 10–14

    Google Scholar 

  8. R. Hameed, W. Qadeer, M. Wachs, O. Azizi, A. Solomatnikov, B.C. Lee, S. Richardson, C. Kozyrakis, M. Horowitz, Understanding sources of inefficiency in general-purpose chips, in Proceedings of the 37th Annual International Symposium on Computer Architecture, ISCA ’10, New York, NY, USA (ACM, 2010), pp. 37–47

    Google Scholar 

  9. J. Leng, T. Hetherington, A.E. Tantawy, S. Gilani, N.S. Kim, T.M. Aamodt, V.J. Reddi, Gpuwattch: enabling energy optimizations in gpgpus, in Proceedings of the 40th Annual International Symposium on Computer Architecture, ISCA ’13, New York, NY, USA (2013, ACM), pp. 487–498

    Google Scholar 

  10. D. Voitsechov, Y. Etsion, Single-graph multiple flows: energy efficient design alternative for gpgpus, in Proceeding of the 41st Annual International Symposium on Computer Architecture, ISCA ’14, Piscataway, NJ, USA (IEEE Press, 2014), pp. 205–216

    Google Scholar 

  11. C.J. Hughes, Single-instruction multiple-data execution, in Synthesis Lectures on Computer Architecture (2015), pp. 1–121

    Google Scholar 

  12. K. Czechowski, V.W. Lee, E. Grochowski, R. Ronen, R. Singhal, R. Vuduc, P. Dube, Improving the energy efficiency of big cores, in Proceeding of the 41st Annual International Symposium on Computer Architecture, ISCA ’14, Piscataway, NJ, USA (IEEE Press, 2014), pp. 493–504

    Google Scholar 

  13. H.J. Lee, K.J. Brown, A.K. Sujeeth, T. Rompf, K. Olukotun, Locality-aware mapping of nested parallel patterns on gpus, in Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, IEEE Micro (2014)

    Google Scholar 

  14. I. Kuon, R. Tessier, J. Rose, Fpga architecture: survey and challenges. Found. Trends Electron. Des. Autom. 2(2), 135–253 (2008)

    Article  Google Scholar 

  15. B.H. Calhoun, J.F. Ryan, S. Khanna, M. Putic, J. Lach, Flexible circuits and architectures for ultralow power. Proc. IEEE 98(2), 267–282 (2010)

    Article  Google Scholar 

  16. I. Bolsens, Programming modern fpgas, international forum on embedded multiprocessor soc, keynote. http://www.xilinx.com/univ/mpsoc2006keynote.pdf (2006)

  17. K.K.W. Poon, S.J.E. Wilton, A. Yan, A detailed power model for field-programmable gate arrays. ACM Trans. Des. Autom. Electron. Syst. 10(2), 279–302 (2005)

    Article  Google Scholar 

  18. V. Adhinarayanan, I. Paul, J.L. Greathouse, W. Huang, A. Pattnaik, W. Feng, Measuring and modeling on-chip interconnect power on real hardware, in 2016 IEEE International Symposium on Workload Characterization (IISWC) (Sept 2016), pp. 1–11

    Google Scholar 

  19. R. Tessier, K. Pocek, A. DeHon, Reconfigurable computing architectures. Proc. IEEE 103(3), 332–354 (2015)

    Article  Google Scholar 

  20. T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk, P.Y.K. Cheung, Reconfigurable computing: architectures and design methods. IEE Proc. Comput. Digit. Tech. 152(2), 193–207 (2005)

    Article  Google Scholar 

  21. R. Hartenstein, A decade of reconfigurable computing: a visionary retrospective, in Proceedings of the Conference on Design, Automation and Test in Europe, DATE ’01, Piscataway, NJ, USA (IEEE Press, 2001), pp. 642–649

    Google Scholar 

  22. R. Prabhakar, Y. Zhang, D. Koeplinger, M. Feldman, T. Zhao, S. Hadjis, A. Pedram, C. Kozyrakis, K. Olukotun, Plasticine: a reconfigurable architecture for parallel patterns, in Proceedings of the 44th Annual International Symposium on Computer Architecture (ACM, 2017), 389–402

    Google Scholar 

  23. T. Zhao, Y. Zhang, K. Olukotun, Serving recurrent neural networks efficiently with a spatial accelerator, in Proceedings of the 2nd SysML Conference (SysML 2019). Palo Alto, CA, USA

    Google Scholar 

  24. J. Fowers, K. Ovtcharov, M. Papamichael, T. Massengill, M. Liu, D. Lo, S. Alkalay, M. Haselman, L. Adams, M. Ghandi, S. Heil, P. Patel, A. Sapek, G. Weisz, L. Woods, S. Lanka, S.K. Reinhardt, A.M. Caulfield, E.S. Chung, D. Burger, A configurable cloud-scale DNN processor for real-time AI, in 45th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2018, Los Angeles, CA, USA

    Google Scholar 

  25. Y. Zhang, A. Rucker, M. Vilim, R. Prabhakar, W. Hwang, K. Olukotun, Scalable interconnects for reconfigurable spatial architectures, in Proceedings of the 46th International Symposium on Computer Architecture (ISCA 2019). Phoenix, AZ, USA

    Google Scholar 

  26. D. Koeplinger, M. Feldman, R. Prabhakar, Y. Zhang, S. Hadjis, R. Fiszel, T. Zhao, L. Nardi, A. Pedram, C. Kozyrakis, K. Olukotun, Spatial: a language and compiler for application accelerators, in Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI 2018) (ACM, New York, NY, USA)

    Google Scholar 

  27. V. Govindaraju, C. Ho, T. Nowatzki, J. Chhugani, N. Satish, K. Sankaralingam, C. Kim, Dyser: unifying functionality and parallelism specialization for energy-efficient computing. IEEE Micro 32(5), 38–51 (2012)

    Article  Google Scholar 

  28. T.J. Callahan, J.R. Hauser, J. Wawrzynek, The garp architecture and c compiler. Computer 33(4), 62–69 (2000)

    Article  Google Scholar 

  29. M. Mishra, T.J. Callahan, T. Chelcea, G. Venkataramani, S.C. Goldstein, M. Budiu, Tartan: evaluating spatial computation for whole program execution, in Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASP-LOS XII, New York, NY, USA (ACM, 2006), pp. 163–174

    Google Scholar 

  30. S.C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R.R. Taylor, R. Laufer, Piperench: a co/processor for streaming multimedia acceleration, in Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA ’99, Washington, DC, USA (IEEE Computer Society, 1999), pp. 28–39

    Google Scholar 

  31. K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D. Burger, S.W. Keckler, C.R. Moore, Exploiting ilp, tlp, and dlp with the polymorphous trips architecture, in Proceedings of the 30th Annual International Symposium on Computer Architecture, ISCA ’03, New York, NY, USA (ACM, 2003), pp. 422–433

    Google Scholar 

  32. Wave Computing Launches Machine Learning Appliance. https://www.top500.org/news/wave-computing-launches-machine-learning-appliance/

  33. J. Noguera, C. Dick, V. Kathail, G. Singh, K. Vissers, R. Wittig, 2018. Xilinx Project Everest: ‘HW/SW Programmable Engine’ (Hot Chips 30). http://www.hotchips.org/hc30/2conf/2.03_Xilinx_Juanjo_XilinxSWPEHotChips20180819.pdf

  34. B. Mei, S. Vernalde, D. Verkest, H. De Man, R. Lauwereins, ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix (Springer, Berlin, 2003), pp. 61–70

    Google Scholar 

  35. P. Gratz, C. Kim, K. Sankaralingam, H. Hanson, P. Shivakumar, S.W. Keckler, D. Burger, On-chip interconnection networks of the trips chip. IEEE Micro 27(5), 41–50 (2007)

    Article  Google Scholar 

  36. M.B. Taylor, J. Kim, J. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffman, P. Johnson, J.W. Lee, W. Lee, A. Ma, A. Saraf, M. Seneski, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, A. Agarwal, The raw microprocessor: a computational fabric for software circuits and general-purpose programs. IEEE Micro 22(2), 25–35 (2002)

    Article  Google Scholar 

  37. D.C. Cronquist, C. Fisher, M. Figueroa, P. Franklin, C. Ebeling, Architecture design of reconfigurable pipelined datapaths, in Proceedings. 20th Anniversary Conference on Advanced Research in VLSI, 1999 (Mar 1999), pp. 23–40

    Google Scholar 

  38. B. Van Essen, A. Wood, A. Carroll, S. Friedman, R. Panda, B. Ylvisaker, C. Ebeling, S. Hauck, Static versus scheduled interconnect in coarse-grained reconfigurable arrays, in 2009 International Conference on Field Programmable Logic and Applications (Aug 2009), pp. 268–275

    Google Scholar 

  39. M. Gao, C. Kozyrakis, Hrl: Efficient and flexible reconfigurable logic for near-data processing, in 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA) (March 2016), pp. 126–137

    Google Scholar 

  40. A. Parashar, M. Pellauer, M. Adler, B. Ahsan, N. Crago, D. Lustig, V. Pavlov, A. Zhai, M. Gambhir, A. Jaleel, R. Allmon, R. Rayess, S. Maresh, J. Emer, Triggered instructions: a control paradigm for spatially-programmed architectures, in Proceedings of the 40th Annual International Symposium on Computer Architecture, ISCA ’13, New York, NY, USA (ACM, 2013), pp. 142–153

    Google Scholar 

  41. S. Swanson, A. Schwerin, M. Mercaldi, A. Petersen, A. Putnam, K. Michelson, M. Oskin, S.J. Eggers, The wavescalar architecture. ACM Trans. Comput. Syst. 25(2), 4:1–4:54 (May 2007)

    Google Scholar 

  42. G. Dimitroulakos, M.D. Galanis, C.E. Goutis, Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures, in Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International (IEEE, 2006), pp. 10

    Google Scholar 

  43. C. Nicol, A coarse grain reconfigurable array (cgra) for statically scheduled data flow computing

    Google Scholar 

  44. M. Karunaratne, A. Kulkarni Mohite, T. Mitra, L.S. Peh, Hycube: a cgra with reconfigurable single-cycle multi-hop interconnect, in Proceedings of the 54th Annual Design Automation Conference 2017, DAC ’17, New York, NY, USA ACM, 2017), pp. 45:1– 45:6

    Google Scholar 

  45. H. Jones, Strategies in optimizing market positions for semiconductor vendors based on ip leverage, ibs white paper. http://www.ibs-inc.net (2014)

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Author information

Authors and Affiliations

  1. SambaNova Systems Inc, Palo Alto, CA, USA

    Raghu Prabhakar

  2. Stanford University, Stanford, CA, USA

    Raghu Prabhakar, Yaqi Zhang & Kunle Olukotun

Authors
  1. Raghu Prabhakar
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  2. Yaqi Zhang
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  3. Kunle Olukotun
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Corresponding author

Correspondence to Raghu Prabhakar .

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Editors and Affiliations

  1. Department of Electrical Engineering, Stanford University, Stanford, CA, USA

    Boris Murmann

  2. Sindelfingen, Baden-Württemberg, Germany

    Bernd Hoefflinger

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Prabhakar, R., Zhang, Y., Olukotun, K. (2020). Coarse-Grained Reconfigurable Architectures. In: Murmann, B., Hoefflinger, B. (eds) NANO-CHIPS 2030. The Frontiers Collection. Springer, Cham. https://doi.org/10.1007/978-3-030-18338-7_14

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