Abstract
Advances in process technology have enabled Field Programmable Gate Arrays (FPGAs) to grow in capacity and implement large heterogenous systems in a monolithic device. With the slowdown of Moore’s law, computer architects now consider domain-specific architectures as the only path left for major improvements in performance-cost-energy. FPGAs are highly adaptable devices, making them the prime candidates for a wide range of emerging domains, including compute-intensive machine learning. Upcoming programmable devices in 7 nm process technology offer a hybrid compute platform that tightly integrates traditional FPGA programmable fabric, multiple CPUs, and an array of reconfigurable vector processors. This platform combines bit-level programmable customization using FPGA-like architecture for ultimate domain optimization with traditional compute using CPUs. Moreover, highly parallelized byte-level processing using CGRA (Coarse Grained Reconfigurable Architecture) is integrated on the same platform. Looking forward, we anticipate that the rising cost of building monolithic devices will also set a disaggregation trend towards using multiple dies. Building systems in the package will provide another cost dimension for programmable devices, further expanding the possibility of new domain-specific architectures and tools. As a consequence of these hardware evolutions, the FPGA tools are also raising the abstraction of design entry with the goal of catering to software programmers and domain experts. We will end the chapter by discussing the automation required for the transition of traditional EDA-like tools to emerging domain-specific compilers for future programmable devices.
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Kaviani, A. (2020). Enabling Domain-Specific Architectures with Programmable Devices. In: Murmann, B., Hoefflinger, B. (eds) NANO-CHIPS 2030. The Frontiers Collection. Springer, Cham. https://doi.org/10.1007/978-3-030-18338-7_13
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DOI: https://doi.org/10.1007/978-3-030-18338-7_13
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