Skip to main content

High-Speed 3D Memories Enabling the AI Future

  • Chapter
  • First Online:
NANO-CHIPS 2030

Part of the book series: The Frontiers Collection ((FRONTCOLL))

  • 2759 Accesses

Abstract

AI (Artificial Intelligence) is all about possessing a high volume of unstructured data and then needing to process it at high speed. DRAM today is the technology of choice for memory in such AI systems. Yet, DRAM’s high energy per bit and the diminishing scaling of DRAM represent a real challenge for the AI system’s future. This chapter covers solutions utilizing technologies similar to those currently used in 3D NAND for high speed memory.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 109.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 149.00
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 139.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. S. Mueller et al., Incipient ferroelectricity in Al-doped HfO2 thin films. Adv. Funct. Mater. 22(11), 2412–2417 (2012)

    Article  Google Scholar 

  2. J. Müller et al., Ferroelectric hafnium oxide: a CMOS-compatible and highly scalable approach to future ferroelectric memories, in 2013 IEEE International Electron Devices Meeting (IEEE, 2013)

    Google Scholar 

  3. H.C. Wann, C. Hu, High-endurance ultra-thin tunnel oxide in MONOS device structure for dynamic memory application. IEEE Electron Device Lett. 16(11), 491–493 (1995)

    Article  ADS  Google Scholar 

  4. H.I. Hanafi et al., A scalable low power vertical memory, in Proceedings of International Electron Devices Meeting (IEEE, 1995)

    Google Scholar 

  5. K. Tsunoda et al., Ultra-high speed direct tunneling memory (DTM) for embedded RAM applications, in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (IEEE, 2004)

    Google Scholar 

  6. Patents: US 7,848,148, US 8,705,278

    Google Scholar 

  7. Patents: US 6,249,460, US 6,639,835, US 6,730,960

    Google Scholar 

  8. J. Cooke, Flash Memory 101: An Introduction to NAND Flash. EE Times, 20 Mar 2006

    Google Scholar 

  9. Patents: US 8,203,187, US 8,426,294

    Google Scholar 

  10. Patents: US 10,014,318 and PCT application WO 2017/053329

    Google Scholar 

  11. Patents: US 9,842,651, US 9,892,800, US 9,911,497

    Google Scholar 

  12. Patent application: WO/2018/144957

    Google Scholar 

  13. S.-J. Choi et al., Performance breakthrough in NOR flash memory with dopant-segregated Schottky-barrier (DSSB) SONOS devices, in 2009 Symposium on VLSI Technology (IEEE, 2009)

    Google Scholar 

  14. S.-J. Choi et al., A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory, in 2010 Symposium on VLSI Technology (IEEE, 2010)

    Google Scholar 

  15. C.-H. Shih et al., Source-side injection Schottky barrier flash memory cells. Semicond. Sci. Technol. 24(2), 025013 (2009)

    Article  ADS  MathSciNet  Google Scholar 

  16. C.-H. Shih et al., Schottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltages. IEEE Electron Device Lett. 32(11), 1477–1479 (2011)

    Article  ADS  Google Scholar 

  17. Y. Noh et al., Synaptic devices based on 3-D AND flash memory architecture for neuromorphic computing, in IEEE International Memory Workshop (IMW) (2019)

    Google Scholar 

  18. H.-T. Lue et al., A novel 3D AND-type NVM architecture capable of high-density, low-power in-memory sum-of-product computation for artificial intelligence application, in 2018 IEEE Symposium on VLSI Technology (IEEE, 2018)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Zvi Or-Bach .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2020 Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Or-Bach, Z. (2020). High-Speed 3D Memories Enabling the AI Future. In: Murmann, B., Hoefflinger, B. (eds) NANO-CHIPS 2030. The Frontiers Collection. Springer, Cham. https://doi.org/10.1007/978-3-030-18338-7_10

Download citation

Publish with us

Policies and ethics