Abstract
High-level synthesis (HLS) is of paramount importance to enable software developers to map critical computations to FPGA-based hardware accelerators. However, in order to generate efficient hardware accelerators one needs to apply significant code transformations and adequately use the directive-driven approach, part of most HLS tools. The code restructuring and directives needed are dependent not only of the characteristics of the input code but also of the HLS tools and target FPGAs. These aspects require a deep knowledge about the subjects involved and tend to exclude software developers. This paper presents our recent approach for automatic code restructuring targeting HLS tools. Our approach uses an unfolded graph representation, which can be generated from program execution traces, and graph-based optimizations, such as folding, to generate suitable HLS C code. In this paper, we describe the approach and the new optimizations proposed. We evaluate the approach with a number of representative kernels and the results show its capability to generating efficient hardware implementations only achievable using manual restructuring of the input software code and manual insertion of adequate HLS directives.
This work was partially supported by the TEC4Growth project.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Nane, R., et al.: A survey and evaluation of FPGA high-level synthesis tools. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 35(10), 1591–1604 (2016)
Cardoso, J.M.P., Weinhardt, M.: High-level synthesis. In: Koch, D., Hannig, F., Ziener, D. (eds.) FPGAs for Software Programmers, pp. 23–47. Springer, Cham (2016). https://doi.org/10.1007/978-3-319-26408-0_2
Ferreira, A.C., Cardoso, J.M.P.: Unfolding and folding: a new approach for code restructuring targeting HLS for FPGAs. In: FSP Workshop 2018: Fifth International Workshop on FPGAs for Software Programmers, Dublin, Ireland, pp. 1–10 (2018)
Tsoutsouras, V., et al.: An exploration framework for efficient high-level synthesis of support vector machines: case study on ECG arrhythmia detection for Xilinx Zynq SoC. J. Sig. Process. Syst. 88(2), 127–147 (2017)
Texas Instrument, TMS320C6000 DSP Library (DSPLIB). Accessed 16 June 2018. http://www.ti.com/tool/sprc265
Lee, C.G.: 15 August 2002. http://www.eecg.toronto.edu/~corinna/. Accessed 16 June 2018
Cardoso, J.M.P., et al.: REFLECT: rendering FPGAs to multi-core embedded computing. In: Cardoso, J., Hübner, M. (eds.) Reconfigurable Computing, pp. 261–289. Springer, New York (2011). https://doi.org/10.1007/978-1-4614-0061-5_11
Xilinx. Vivado design suite user guide: high level synthesis, 20 December 2017
Cong, J., Huang, M., Pan, P., Wang, Y., Zhang, P.: Source-to-source optimization for HLS. In: Koch, D., Hannig, F., Ziener, D. (eds.) FPGAs for Software Programmers, pp. 137–163. Springer, Cham (2016). https://doi.org/10.1007/978-3-319-26408-0_8
Cardoso, J.M.P., et al.: Specifying compiler strategies for FPGA-based systems. In: 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, pp. 192–199, April 2012
Canis, A., et al.: LegUP: an open-source high-level synthesis tool for FPGA-based processor/accelerator systems. ACM Trans. Embed. Comput. Syst. 13(2), 24:1–24:27 (2013)
LLVM. The LLVM compiler infrastructure project (2018). https://llvm.org
Mencer, O.: ASC: a stream compiler for computing with FPGAs. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 25(9), 1603–1617 (2006)
Maxeler Technologies. Maxcompiler white paper (2017)
Voss, N., et al.: Automated dataflow graph merging. In: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2016), pp. 219–226, July 2016
Bondhugula, U., Hartono, A., Ramanujam, J., Sadayappan, P.: A practical automatic polyhedral parallelizer and locality optimizer. In: Proceedings of the 29th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI 2008), pp. 101–113. ACM, New York (2008)
Zuo, W., Liang, Y., Li, P., Rupnow, K., Chen, D., Cong, J.: Improving high level synthesis optimization opportunity through polyhedral transformations. In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2013). ACM, New York, pp. 9–18 (2013)
Morvan, A., Derrien, S., Quinton, P.: Polyhedral bubble insertion: a method to improve nested loop pipelining for high-level synthesis. Trans. Comput.-Aided Des. Integr. Circ. Syst. 32(3), 339–352 (2013)
Acknowledgments
This work was partially funded by the project “NORTE-01-0145-FEDER-000020", financed by the North Portugal Regional Operational Programme under the PORTUGAL 2020 Partnership Agreement, and through the European Regional Development Fund (ERDF) through the Operational Programme for Competitiveness and Internationalisation - COMPETE 2020 Programme, and by National Funds through the Portuguese funding agency, FCT - Fundação para a Ciência e a Tecnologia within project POCI-01-0145-FEDER-016883.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this paper
Cite this paper
Ferreira, A.C., Cardoso, J.M.P. (2019). Graph-Based Code Restructuring Targeting HLS for FPGAs. In: Hochberger, C., Nelson, B., Koch, A., Woods, R., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2019. Lecture Notes in Computer Science(), vol 11444. Springer, Cham. https://doi.org/10.1007/978-3-030-17227-5_17
Download citation
DOI: https://doi.org/10.1007/978-3-030-17227-5_17
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-17226-8
Online ISBN: 978-3-030-17227-5
eBook Packages: Computer ScienceComputer Science (R0)