Skip to main content

Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging

  • Conference paper
  • First Online:
Applied Reconfigurable Computing (ARC 2019)

Abstract

In this research work, an on-board dual-core embedded architecture was developed for SAR imaging systems, implementing a reduced-precision redundancy fault-tolerance mechanism. This architecture protects the execution of the BackProjection Algorithm, capable of generating acceptable SAR images in embedded systems subjected to errors from the space environment. The proposed solution was implemented on a Xilinx SoC device with a dual-core processor. The present work was able to produced images with less 0.65 dB on average, than the fault-free image, at the expense of a time overhead up to 33%, when in the presence of error rates similar to the ones measured in space environment. Notwithstanding, the BackProjection algorithm executed up to 1.58 times faster than its single-core version without any fault-tolerance mechanisms.

This work was supported by national funds through Fundação para a Ciencia e a Tecnologia (FCT) with reference UID/CEC/50021/2019, and project SARRROCA, “Synthetic Aperture Radar Robust Reconfigurable Optimized Computing Architecture” with reference: PTDC/EEI-HAC/31819/2017, funded by FCT/MCTES through national funds, and POCI - Programa Operacional Competitividade e Internacionalização e PORLisboa - Programa Operacional Regional de Lisboa.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html.

  2. 2.

    https://ftp.gnu.org/old-gnu/Manuals/gprof-2.9.1/html_mono/gprof.html.

  3. 3.

    https://www.atwillys.de/content/cc/sine-lookup-for-embedded-in-c/.

  4. 4.

    https://github.com/PetteriAimonen/libfixmath.

  5. 5.

    https://people.sc.fsu.edu/~jburkardt/c_src/cordic/cordic.html.

  6. 6.

    http://herschel.esac.esa.int/Docs/Herschel/html/ch04s02.html.

References

  1. Barker, K., et al.: PERFECT (Power Efficiency Revolution For Embedded Computing Technologies) Benchmark Suite Manual. Pacific Northwest National Laboratory and Georgia Tech Research Institute, December 2013. http://hpc.pnnl.gov/projects/PERFECT/

  2. Baumann, R.C.: Radiation-induced soft errors in advanced semiconductor technologies. IEEE Trans. Device Mater. Reliab. 5(3), 305–316 (2005). https://doi.org/10.1109/TDMR.2005.853449

    Article  Google Scholar 

  3. Claeys, C., Simoen, E.: Radiation Effects in Advanced Semiconductor Materials and Devices. Springer, Heidelberg (2002). https://doi.org/10.1007/978-3-662-04974-7

    Book  Google Scholar 

  4. Duarte, R.P., Bouganis, C.: Zero-latency datapath error correction framework for over-clocking DSP applications on FPGAs. In: 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14), pp. 1–7, Deceember 2014. https://doi.org/10.1109/ReConFig.2014.7032566

  5. Duarte, R.P., Bouganis, C.S.: High-level linear projection circuit design optimization framework for FPGAs under over-clocking. In: 2012 22nd International Conference on Field Programmable Logic and Applications (FPL), pp. 723–726. IEEE (2012)

    Google Scholar 

  6. Duarte, R.P., Bouganis, C.-S.: A unified framework for over-clocking linear projections on FPGAs under PVT variation. In: Goehringer, D., Santambrogio, M.D., Cardoso, J.M.P., Bertels, K. (eds.) ARC 2014. LNCS, vol. 8405, pp. 49–60. Springer, Cham (2014). https://doi.org/10.1007/978-3-319-05960-0_5

    Chapter  Google Scholar 

  7. Duarte, R.P., Bouganis, C.S.: ARC 2014 over-clocking KLT designs on FPGAs under process, voltage, and temperature variation. ACM Trans. Reconfigurable Technol. Syst. 9(1), 7:1–7:17 (2015). https://doi.org/10.1145/2818380

    Article  Google Scholar 

  8. Fang, W.C., Le, C., Taft, S.: On-board fault-tolerant SAR processor for spaceborne imaging radar systems. In: 2005 IEEE International Symposium on Circuits and Systems, vol. 1, pp. 420–423, May 2005. https://doi.org/10.1109/ISCAS.2005.1464614

  9. Ganssle, J.: The Firmware Handbook. Academic Press Inc., Orlando (2004)

    Google Scholar 

  10. Jacobs, A., Cieslewski, G., Reardon, C., George, A.: Multiparadigm computing for space-based synthetic aperture radar (2008)

    Google Scholar 

  11. Maki, A.: Space radiation effect on satellites. Joho Tsushin Kenkyu Kiko Kiho 55(1–4), 43–48 (2009)

    Google Scholar 

  12. Pratt, B., Fuller, M., Wirthlin, M.: Reduced-precision redundancy on FPGAs (2011). https://doi.org/10.1155/2011/897189

    Article  Google Scholar 

  13. Pritsker, D.: Efficient global back-projection on an FPGA. In: 2015 IEEE Radar Conference (RadarCon), pp. 0204–0209, May 2015. https://doi.org/10.1109/RADAR.2015.7130996

  14. Sinclair, D., Dyer, J.: Radiation effects and cots parts in smallsats (2013)

    Google Scholar 

  15. Sørensen, J., Santin, G.: The radiation environment and effects for future ESA cosmic vision missions. In: 2009 European Conference on Radiation and Its Effects on Components and Systems, pp. 356–363, September 2009. https://doi.org/10.1109/RADECS.2009.5994676

  16. Tambara, L.A.: Analyzing the impact of radiation-induced failures in all programmable system-on-chip devices (2017)

    Google Scholar 

  17. Ullah, A., Reviriego, P., Pontarelli, S., Maestro, J.A.: Majority voting-based reduced precision redundancy adders. IEEE Trans. Device Mater. Reliab. PP(99), 1 (2017). https://doi.org/10.1109/TDMR.2017.2781186

    Article  Google Scholar 

  18. Volder, J.: The cordic computing technique. In: Papers Presented at the 3–5 March 1959, Western Joint Computer Conference, IRE-AIEE-ACM 1959 (Western), pp. 257–261. ACM, New York (1959). https://doi.org/10.1145/1457838.1457886

  19. Wang, S.J., Jha, N.K.: Algorithm-based fault tolerance for FFT networks. IEEE Trans. Comput. 43(7), 849–854 (1994). https://doi.org/10.1109/12.293265

    Article  MATH  Google Scholar 

  20. Ya’acob, N., Zainudin, A., Magdugal, R., Naim, N.F.: Mitigation of space radiation effects on satellites at low earth orbit (LEO). In: 2016 6th IEEE International Conference on Control System, Computing and Engineering (ICCSCE), pp. 56–61, November 2016. https://doi.org/10.1109/ICCSCE.2016.7893545

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Rui Policarpo Duarte .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer Nature Switzerland AG

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Cruz, H., Duarte, R.P., Neto, H. (2019). Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging. In: Hochberger, C., Nelson, B., Koch, A., Woods, R., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2019. Lecture Notes in Computer Science(), vol 11444. Springer, Cham. https://doi.org/10.1007/978-3-030-17227-5_1

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-17227-5_1

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-17226-8

  • Online ISBN: 978-3-030-17227-5

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics