Evaluation of the Prototype

  • Mauro SantosEmail author
  • Jorge Guilherme
  • Nuno Horta
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 558)


This Chapter details the custom hardware test platform and test software that was developed to evaluate the demonstrator prototype. Experimental results will be presented and compared with the simulation results obtained previously. The experimental results will also be compared with other converters presented in the literature, both logarithmic converters and linear converter.


  1. 1.
    S.-F. Chen, Y.-J. Juang, S.-Y. Huang, and Y.-C. King, Logarithmic CMOS image sensor through multi-resolution analog-to-digital conversion, in International Symposium on VLSI Technology, Systems and Applications, 2003, pp. 227–230Google Scholar
  2. 2.
    J. Mahattanakul, Logarithmic data converter suitable for hearing aid applications. Electronic Letters 41(7), 394–396 (2005)CrossRefGoogle Scholar
  3. 3.
    J. Lee et al., A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC. IEEE J. Solid-State Circ. 44(10), 2755–2765 (2009)CrossRefGoogle Scholar
  4. 4.
    J. Guo and S. Sonkusale, Current-mode readout cicuits with pixel-level logarithmic ADC for IR FPA applications, in 51st Midwest Symposium on Circuits and Systems, Knoxville, TN, 2008, pp. 394–397Google Scholar
  5. 5.
    S. Sirimasakul, A. Thanachayanont, and W. Jeamsaksiri, Low-power current-mode logarithmic pipeline analog-to-digital converter for ISFET based pH sensor, in 9th International Symposium on Communications and Information Technology, Icheon, 2009, pp. 1340–1343Google Scholar
  6. 6.
    J. Guo, S. Sonkusale, An area-efficient and low-power logarithmic A/D converter for current-mode sensor array. IEEE Sens. J. 9(12), 2042–2043 (2009)CrossRefGoogle Scholar
  7. 7.
    D. Kim, M. Song, An enhanced dynamic-range CMOS image sensor using a digital logarithmic single-slope ADC. IEEE Trans. Circuits Syst. II Express Briefs 50(10), 653–657 (2012)CrossRefGoogle Scholar
  8. 8.
    X. Zhu, Y. Chen, S. Tsukamoto, and T. Kuroda, A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array, in Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, Hsinchu, 2012, pp. 1–4Google Scholar
  9. 9.
    R. Rajendran and P. V. Ramakrishna, A Design of 6-bit 125-MS/s SAR ADC in 0.13-µm MM/RF CMOS Process, in 2012 International Symposium on Electronic System Design (ISED), Kolkata, 2012, pp. 23–27Google Scholar
  10. 10.
    Y. Tao, Y. Lian, A 0.8-V, 1-MS/s, 10-bit SAR ADC for Multi-Channel Neural Recording. IEEE Trans. Circuits Syst. I Regul. Pap. 62(2), 366–375 (2015)CrossRefGoogle Scholar
  11. 11.
    R. Długosz and G. Fischer, Low chip area, low power dissipation, programmable, current mode, 10-bits, SAR ADC implemented in the CMOS 130 nm technology, in 2015 22nd International Conference Mixed Design of Integrated Circuits &Systems (MIXDES), Torun, 2015, pp. 348–353Google Scholar
  12. 12.
    T. Rabuske and J. Fernandes, A 9-b 0.4-V charge-mode SAR ADC with 1.6-V input swing and a MOSCAP-only DAC, in ESSCIRC Conference 2015—41st European Solid-State Circuits Conference (ESSCIRC), Graz, 2015, pp. 311–314Google Scholar
  13. 13.
    C. Chen and B. Wang, An ultra low power 10-bit 1KS SAR-ADC for ECG signal recording applications, in 2016 China Semiconductor Technology International Conference (CSTIC), Shanghai, 2016, pp. 1–4Google Scholar
  14. 14.
    J. Lee et al., A 2.5 mW 80 dB DR 36 dB SNDR 22MS/s Logarithmic Pipeline ADC, in IEEE Symposium on VLSI Circuits, Kyoto, 2007, pp. 194–195 Google Scholar
  15. 15.
    L. Hernandez and A.S. Paton, A continuous-time noise-shaping modulator for logarithmic A/D conversion, in IEEE International Symposium on Circuits and Systems, Orlando, FL, 1999, pp. 364–367Google Scholar
  16. 16.
    S. Kumar and S. Chatterjee, A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time ΔΣ Modulator for Audio Applications, in International Conference on VLSI Design, Hyderabad, 2012, pp. 51–56Google Scholar
  17. 17.
    L. Hernandez and A.S. Paton, Noise shaping modulator with logarithmic response. Electron. Lett. 35, 12, 955–956 (1999)Google Scholar
  18. 18.
    J. Guilherme, J. Vital, and J.E. Franca, New logarithmic two-step flash A/D converter with digital error correction for MOS technology, in 38th Midwest Symposium on Circuits and Systems, Rio de Janeiro, 1995, pp. 881–884Google Scholar
  19. 19.
    F. Chen and C.S. Chen, A 20 b dynamic-range floating-point data acquisition system. IEEE Trans. Indus. Electron. 38, 1, 10–14 (1991)Google Scholar
  20. 20.
    T. Nguyen, S. Zupancic, and D.Y.C. Lie, Engineering Challenges in Cochlear Implants Design and Practice. IEEE Circ. Syst. Mag. 12, 4, 47–55, (2012). (Fourthquarter)Google Scholar
  21. 21.
    M. Sadaghdar, K. Iniewski, M. Syrzycki, 11-bit floating-point pipelined analog to digital converter in 0.18 μm CMOS, in Canadian Conference on Electrical and Computer Engineering, 2004, pp. 1503–1506Google Scholar
  22. 22.
    D.U. Thompson, B.A. Wooley, A 15-b pipelined CMOS floating-point A/D converter. IEEE J. Solid-State Circuits 36(2), 299–303 (2001)CrossRefGoogle Scholar
  23. 23.
    V.Z. Groza, High-resolution floating-point ADC. IEEE Trans. Instrum. Meas. 50(6), 1822–1829 (2001)CrossRefGoogle Scholar
  24. 24.
    Y.-S. Shu, M.-J. Kyung, W.-M. Lee, B.-S. Song, and B. Pain, A 10 ∼ 15b 60MS/s floating-point ADC with digital gain and offset calibration, in IEEE Custom Integrated Circuits Conference, San Jose, CA, 2008, pp. 157–160Google Scholar
  25. 25.
    J. Piper and J. Yuan, Design considerations of a floating-point ADC with embedded S/H, in IEEE International Symposium on Circuits and Systems, 2005, pp. 6166–6169Google Scholar
  26. 26.
    J.M.D. Pereira, O. Postolache, and P.S. Girao, “PWM-A/D conversion: a flexible and low-cost solution for transducer linearization, in Proceedings of the First ISA/IEEE Conference Sensors for Industry, Rosemont, IL, 2001, pp. 258–263Google Scholar
  27. 27.
    B. Lienert, J. Porter, N. Ahlquist, D. Harris, and S. Sharma, A 50 MHz logarithmic amplifier for use in lidar measurements, in IEEE International Geoscience and Remote Sensing Symposium, Sydney, NSW, 2001, pp. 2914–2915.Google Scholar
  28. 28.
    J. Guilherme, Architectures for High Dynamic Range CMOS Pipeline Analogue-to-Digital Signal Conversion, Ph.D. dissertation, Universidade Técnica de Lisboa, Instituto Superior Técnico, Lisbon, Portugal, 2003Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Synopsys Portugal LdaPorto SalvoPortugal
  2. 2.Instituto Superior TécnicoInstituto TelecomunicaçõesLisbonPortugal
  3. 3.Instituto Superior TécnicoInstituto TelecomunicaçõesLisbonPortugal

Personalised recommendations