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High-Voltage and Power Transistors

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Abstract

This chapter focuses mainly on the drain-extended MOS (DEMOS) transistor and on the lateral double-diffused MOS (LDMOS) transistor for high-voltage/high-power applications. In both cases, the drain is extended with a lightly doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation (QS), body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications.

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Notes

  1. 1.

    Epitaxy is the process of growing a single-crystal film on a single-crystal substrate.

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Author information

Authors and Affiliations

  1. PIYE, Cedar Park, TX, USA

    Badih El-Kareh

  2. Lou Hutter Consulting, Dallas, TX, USA

    Lou N. Hutter

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Problems

Problems

  1. 1.

    The channel length of the intrinsic MOSFET in a DENMOS is 1 μm and the drift length 4 μm. Assume velocity saturation in both the MOSFET and drift region, and find the time of flight for an electron to travel from source to drain.

  2. 2.

    The channel width of a DENMOS is 1 cm, and the off-current at 25 °C is measured as 1 pA/μm. Assume an ideality factor of 1.4 and a decrease in VT of 1 mV/°C as the temperature increases from 25 to 125 °C, and calculate the off-current at 125 °C. Neglect the thermally generated current.

  3. 3.

    For a DENMOS having a device pitch of 4.45 μm and an RSP = 20 mΩ-mm2, find the device width needed to achieve RDS(on) = 1 Ω.

  4. 4.

    In a planar LDMOS, the gate overlap of the N-drift region is 0.5 μm, the gate oxide thickness is 15 nm, the threshold voltage is 0.7 V, the device width is 1 cm, and the fringe capacitance between gate and N-drift region is 0.25 fF/μm. The gate is charged with a constant current of 1 mA. Estimate the time-span of the Miller plateau.

  5. 5.

    The following LDMOS information is given: intrinsic MOSFET tox = 12.5 nm, Leff = 1 μm, VT = 0.7 V, device width = 20 μm, tdrift = 1.5 μm, Ldrift = 2 μm, and ND = 2 × 1016 cm−3. Approximate the gate voltage at the onset of the Kirk effect in the drift region. Assume that at that point, the MOSFET operates in saturation, μeff = 300 cm2/Vs, and the temperature is 25 °C.

  6. 6.

    At what drain voltage will avalanche breakdown occur in the structure below? Assume a critical field of 3 × 105 V/cm and 25 °C.

    figure 62
  7. 7.

    The structure in the figure below was subjected to hot-electron stress during which electrons were trapped in the STI at the interface with the N-drift region. Assume that the trapped electrons are uniformly distributed at a concentration of 5 × 1011 cm−2. For 25 °C, estimate

    1. (a)

      The N-drift sheet resistance in the portion under the sheet of trapped electrons and under the portion covered by the poly gate

    2. (b)

      The drift resistance under the STI for a device width of 1 cm

      figure 63
  8. 8.

    Calculate the room temperature depletion width and the peak field in silicon in the N-drift region beneath the polysilicon plate, under the STI and at the N-drift-to-P-substrate junction shown in the figure below.

    figure 64
  9. 9.

    For the planar NLDMOS in the figure below, assume Ldrift = 2 μm, Lacc = 0.5 μm, tdrift = 1.3 μm, Leff = 1.0 μm, Weff = 20 μm, tox = 15 nm, and no gate oxide charge. (a) Estimate the room temperature drift resistance for VG at flatband. (b) Estimate RDS(on) for VG = +5 V at 25 and 140 °C. Hint: for surface mobility, use the universal mobility plots in Chap. 6.

    figure 65
  10. 10.

    Consider a 24-V NLDMOS power switch that should carry 10 A and must operate from −40 to +125 °C. The voltage drop across the structure may not exceed 0.5 V. The breakdown voltage, BVDSS, follows a normal distribution with σ = 0.5 V and has a temperature coefficient of 1500 ppm/°C. Assume 10% variation in the power supply voltage, 15% tolerant to RDS(on), and a device pitch of 3.25 μm. For a Six Sigma design, estimate the minimum width of the NLDMOS that should be designed to satisfy the above conditions.

  11. 11.

    For an LDMOS of the type shown in Fig. 7.7, assume ND-drift = 5 × 1016 cm−3, tdrift = 1.5 μm, NA-body = 5 × 1016 cm−3, NA-SUB = 1015 cm−3, and no interaction with the MOS region. Determine

    1. (a)

      If this structure can achieve optimum RESURF (region II in Fig. 7.12)

    2. (b)

      The lateral (P-body/N-drift) breakdown voltage

  12. 12.

    For the structure of the type in Fig. 7.7, determine the required P-substrate doping, Nsub, to achieve optimum RESURF assuming ND = 7 × 1016 cm−3 in the drift region and tdrift = 2 μm.

  13. 13.

    The intrinsic MOSFET in an LDMOS is designed with tox = 12.5 nm, Leff = 0.6 μm, Weff = 10 μm, uniform body concentration NA = 2 × 1017 cm−3, and N+-poly gate. For VG = 5 V, at what temperature T will dID/dT ≈ 0?

  14. 14.

    Explain why a MOSFET with a laterally graded channel as in NLDMOS exhibits a sharper peak in transconductance than a conventional NMOS having a laterally uniform channel.

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El-Kareh, B., Hutter, L.N. (2020). High-Voltage and Power Transistors. In: Silicon Analog Components. Springer, Cham. https://doi.org/10.1007/978-3-030-15085-3_7

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