Multi-chip Modules and Multi-chip Packaging

Abstract

In the previous chapter, the concept of the SoC, where all system circuitry is placed on one die, and that die is packaged, was discussed. It was stated that SoC packaging is often favored above other packaging approaches because of the small form factor that is relatively simply achieved. Numerous reasons, on the other hand, can be listed why one would like to use multiple dice (Some sources also use “dies” and “die” as plural forms of cut wafer die.) in one package. For example, the dice could be fabricated in different technologies (as discussed in Chap. 1) and packaging of these dice in a single package would still be less expensive than packaging the different dice separately. Interconnects inside such packages are also shorter, which is a clear benefit for RF. Dice fabricated in the same or similar technologies (e.g. both CMOS) but packaged in the same enclosure could also offer advantages—for example, one die could hold proprietary circuitry sourced from a third party and the second die could have custom-designed circuitry. In the third example, one could consider multiple identical dice that are stacked in three dimensions and packaged together. Arranging dice in a 3D configuration saves a lot of horizontal space—e.g. stacking four ICs on top of one another could theoretically cut both the width and length of the package by half. This solution may be beneficial for memory circuitry, for example, where a large number of transistors need to be placed in limited space. Stacking does not necessarily require the dice to be identical, but having non-identical dice does complicate the design methodology. However, the approach of 3D stacking of different dice is also often seen in the literature.