Abstract
Since core counts are rising faster than memory transfer rates, subsequent generations of multicore servers will inherently suffer from an ever-widening bandwidth gap if their system architectures are not suitably enhanced. Leading vendors typically handle this well-known issue by supporting the fastest memory rates that are feasible and raising the memory bandwidth by providing additional memory channels in their succeeding server generations. Although several papers address the memory bandwidth gap and ways to ameliorate it, no paper discusses it quantitatively. Our paper focuses on this point by deriving a scaling rule for the memory bandwidth of multicore servers with respect to the core count for preserving the per-core memory-bandwidth over technology generations in a high-end server family. The number of memory channels implemented in Intel’s, AMD’s and IBM’s high-end server lines show a good correlation with results obtained from the square-root rule.
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Sima, D. (2020). The Square-Root Rule for Scaling Memory Channels in Servers. In: Kovács, L., Haidegger, T., Szakál, A. (eds) Recent Advances in Intelligent Engineering. Topics in Intelligent Engineering and Informatics, vol 14. Springer, Cham. https://doi.org/10.1007/978-3-030-14350-3_3
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DOI: https://doi.org/10.1007/978-3-030-14350-3_3
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