Library Pruning for Power Saving During Timing and Electrical Design Rules Optimization
Timing optimization techniques are widely used to meet the frequency and electrical design rules requirement of integrated circuits, they use logical and physical transformation to speed up the problematic signals and to close the design setup and hold constraints. On the other side, each technique induces a power increase as a cost for signal speed up. In this paper, we propose a standard cell library tuning methodology to reduce the timing optimization impact on power increase. We divide each optimization step of the place and route process into two sub-steps, the first one uses only low power standard library cells and try to correct the maximum number of violations, and the second uses all the available cells in the library to close the remaining violations. Experimental results on 45 industrial designs of different processes show that the proposed methodology provides a leakage power reduction of 5%, a total power reduction of 1.3% and a timing improvement of 55.8% in Total Negative Slack and 37.5% in Worst Negative Slack.
KeywordsLibrary pruning Timing optimization CMOS Electrical Design Rule Constraints Electronic design automation System on Chip Physical design Place & route Power optimization
This research was supported by Mentor Graphics Corporation. We thank our colleagues from CDS division who provided insight and expertise that greatly assisted the research, although they may not agree with all of the interpretations/conclusions of this paper.
We thank Dr. Hazem El Tahawy (Mentor Graphics, Managing Director MENA Region) for initiating and supporting this work, Chinnery David (Architect, CSD Nitro R&D Optimization) for assistance, help and guidelines through the research, and Bhardwaj Sarvesh (Group Architect, ICDS P&R Solutions Optimization) for the opportunity to work on such advanced topic.
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