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International Workshop on Parallel Tools for High Performance Computing

PTHPC 2017: Tools for High Performance Computing 2017 pp 17–37Cite as

Counter Inspection Toolkit: Making Sense Out of Hardware Performance Events

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Abstract

Hardware counters play an essential role in understanding the behavior of performance-critical applications, and inform any effort to identify opportunities for performance optimization. However, because modern hardware is becoming increasingly complex, the number of counters that are offered by the vendors increases and, in some cases, so does their complexity. In this paper we present a toolkit that aims to assist application developers invested in performance analysis by automatically categorizing and disambiguating performance counters. We present and discuss the set of microbenchmarks and analyses that we developed as part of our toolkit. We explain why they work and discuss the non-obvious reasons why some of our early benchmarks and analyses did not work in an effort to share with the rest of the community the wisdom we acquired from negative results.

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Notes

  1. 1.

    The actual count is not zero, but rather a small number due to noise caused by code not shown in the figures, such as the calls to PAPI_start() and PAPI_stop(). However, in our experiments this number did not grow when varying the variable size, so for large iteration counts the fraction of mispredicted branches approaches zero.

  2. 2.

    Other, more sophisticated goodness functions, such as Pearson’s \(\chi ^2\) test [7], could be used to assist in the analysis of the measurements, but in our experiments we found that the simple formula in Eq. 1 is sufficient.

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Acknowledgements

This material is based upon work supported by the National Science Foundation under Grant No. 1450429.

Author information

Authors and Affiliations

  1. Innovative Computing Laboratory, University of Tennessee, 1122 Volunteer Blvd, Knoxville, TN, 37996, USA

    Anthony Danalis, Heike Jagode & Jack Dongarra

  2. Mathworks, 7700 Gleason drive, Apt 23D, Knoxville, TN, 37919, USA

    Hanumantharayappa

  3. Cerebras Systems, 428 Madera Ave, apt 5, Sunnyvale, CA, 94086, USA

    Sangamesh Ragate

Authors
  1. Anthony Danalis
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  2. Heike Jagode
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  3. Hanumantharayappa
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  4. Sangamesh Ragate
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  5. Jack Dongarra
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Corresponding author

Correspondence to Anthony Danalis .

Editor information

Editors and Affiliations

  1. Höchstleistungsrechenzentrum Stuttgart (HLRS), Universität Stuttgart, Stuttgart, Germany

    Christoph Niethammer

  2. Höchstleistungsrechenzentrum Stuttgart (HLRS), Universität Stuttgart, Stuttgart, Germany

    Michael M. Resch

  3. Zentrum für Informationsdienste und Hochleistungsrechnen (ZIH), Technische Universität Dresden, Dresden, Germany

    Wolfgang E. Nagel

  4. Zentrum für Informationsdienste und Hochleistungsrechnen (ZIH), Technische Universität Dresden, Dresden, Germany

    Holger Brunst

  5. Zentrum für Informationsdienste und Hochleistungsrechnen (ZIH), Technische Universität Dresden, Dresden, Germany

    Hartmut Mix

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Danalis, A., Jagode, H., Hanumantharayappa, Ragate, S., Dongarra, J. (2019). Counter Inspection Toolkit: Making Sense Out of Hardware Performance Events. In: Niethammer, C., Resch, M., Nagel, W., Brunst, H., Mix, H. (eds) Tools for High Performance Computing 2017. PTHPC 2017. Springer, Cham. https://doi.org/10.1007/978-3-030-11987-4_2

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