Abstract
Thanks to the extreme connectedness of today’s world, it is easier than ever to transfer information and to communicate (The quality of information content is out of this book’s scope.). Wireless links normally use transceivers with a local oscillator in their heart that is typically implemented as a PLL. Reliable and pristine PLL output frequency beat is of crucial importance for the efficient spectrum usage—and higher-order modulation schemes (at large bandwidths) are required to satisfy the end-users growing hunger for fast data throughput. The PLL’s phase noise and spurious content indeed impose the fundamental limit to the density with which the information can be transmitted. Besides the exclusive LO generation, a PLL can be the basis for compact and power-efficient polar transmission. Polar TX architecture is an attractive, digitally intensive solution that simultaneously comes with a set of severe design challenges (such as bandwidth limitation and linearity) that need to be carefully tackled when targeting high-speed communication. This book offers contributions to the state of the art in fractional frequency synthesis and polar transmitter design. The presented material is built around three 28-nm bulk CMOS IC prototypes that investigate and push the boundaries of the field.
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- 1.
The quality of information content is out of this book’s scope.
- 2.
Summarizing future work hopefully helps with letting go of the book writing, for the curse of it could always be better… is not an easy one to confront. I hope that the paragraphs written here fall into a view of someone who can still get the opportunity to walk the paths that we had no time for.
- 3.
The effect becomes increasingly complex in the presence of memory effects, i.e., if the induced error is not instantaneous but it depends on certain amount of previous AM samples.
References
W. Wu, R.B. Staszewski, J.R. Long, A 56.4-to-63.4 GHz multi-rate all-digital fractional-N PLL for FMCW radar applications in 65 nm CMOS. IEEE J. Solid State Circuits 49(5), 1081–1096 (2014)
H. Yeo, S. Ryu, Y. Lee, S. Son, J. Kim, 13.1 A 940MHz-bandwidth 28.8 μs-period 8.9 GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications, in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (IEEE, Piscataway, 2016), pp. 238–239
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Markulic, N., Raczkowski, K., Craninckx, J., Wambacq, P. (2019). Conclusion and Future Outlook. In: Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-030-10958-5_5
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DOI: https://doi.org/10.1007/978-3-030-10958-5_5
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