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Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission pp 85–125Cite as

A Background-Calibrated Digital Subsampling Polar Transmitter

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Part of the book series: Analog Circuits and Signal Processing ((ACSP))

Abstract

In this chapter we present a transmitter, implemented in 28 nm CMOS, which incorporates a low-noise subsampling PLL for phase modulation (PM) and a harmonic rejection mixed inverse class-D digital power amplifier for amplitude modulation (AM). Unlike in a classical polar transmitter, the amplitude modulation happens within the phase lock in this system. As shown throughout the chapter, this specific feature enables background AM-to-AM nonlinearity cancellation, and inherits suppression of AM-to-PM induced distortion. To emphasize this specific property which is a consequence of direct sampling at the transmitter output, we name the architecture subsampling polar transmitter (SSPTX). The chip operates from a 0.9 V supply at 5.5 GHz with 2.5 MHz BW and 1024 QAM with average 1.1 dBm output power, and total power consumption of 50 mW. The proposed SSPTX enables extreme spectral efficiency, outperforming similar art in the field. The explored architecture reveals new opportunities in digital TX solutions for next generation wireless links.

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Notes

  1. 1.

    An obvious way to improve the far-out noise is to use a higher clock speed for the phase modulating DAC, more than the 40 MHz crystal oscillator reference used now.

  2. 2.

    Theoretically this clipping can still appear, however, it is statistically a very rare event that does not influence the average EVM.

  3. 3.

    FOMPLL = \(10\log _{10}\left [\left (\frac {\text{P}_{\text{DC}}}{1 \text{mW}}\right )\left ( \frac {\text{RMS}_{\text{jitter}}}{1 \text{s}} \right )^2\right ]\) as defined in [Gao09a].

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Authors and Affiliations

  1. IMEC, Leuven, Belgium

    Nereo Markulic, Kuba Raczkowski, Jan Craninckx & Piet Wambacq

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  1. Nereo Markulic
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Markulic, N., Raczkowski, K., Craninckx, J., Wambacq, P. (2019). A Background-Calibrated Digital Subsampling Polar Transmitter. In: Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-030-10958-5_4

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  • DOI: https://doi.org/10.1007/978-3-030-10958-5_4

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