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A Background-Calibrated Subsampling PLL for Phase/Frequency Modulation

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Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

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Abstract

In this chapter, we present a DTC-based fractional-N subsampling PLL that operates without performance gap between integer-N and fractional-N modes. This is achieved thanks to the digital background cancellation of nonlinearities in the PLL phase-error comparison path. This −247-dB FOM PLL is further enhanced for two-point, wideband phase modulation, achieving <−40-dB EVM around a 10-GHz carrier during 10-Mb/s GMSK modulation. Analog nonidealities, such as gain imbalance or nonlinearity in the digital-to-modulated phase conversion, are background cancelled, ensuring robust operation with PVT. This system demonstrates state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.

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Notes

  1. 1.

    Alternatively, it is possible to track the sampled voltage. However, in the presence of transconductor offset, the sampled voltage is no longer a valid representation of the phase error. The Type-2 Subsampling loop settles in a zero-phase-offset condition which translates to a zero-current state and not in the zero-sampled-voltage state [Gao10].

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Authors and Affiliations

  1. IMEC, Leuven, Belgium

    Nereo Markulic, Kuba Raczkowski, Jan Craninckx & Piet Wambacq

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  1. Nereo Markulic
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  2. Kuba Raczkowski
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  3. Jan Craninckx
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  4. Piet Wambacq
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Markulic, N., Raczkowski, K., Craninckx, J., Wambacq, P. (2019). A Background-Calibrated Subsampling PLL for Phase/Frequency Modulation. In: Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-030-10958-5_3

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  • DOI: https://doi.org/10.1007/978-3-030-10958-5_3

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  • Online ISBN: 978-3-030-10958-5

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