Abstract
This chapter introduces a local oscillator (LO) as a building block that finds place in the hearth of every modern wireless transceiver. Initially, we discuss the LO performance metrics such as phase noise, spurious content, frequency granularity, and power consumption in context of down/up conversion in accurate receive and transmit modes. An LO is typically implemented within a phase-locked loop (PLL), a system that has been intensively researched for a number of years. We follow its development from initial, purely analog implementations to modern digitally intensive solutions. We discuss the basic theory of operation with practical implementation in mind. The discussion gradually arrives to recently introduced subsampling PLL architectures that tend to overcome typical performance limitations of prior art, offering extreme low-noise synthesis potential.
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Notes
- 1.
A direct conversion, i.e., zero-Intermediate Frequency (IF) transceiver is depicted in this example.
- 2.
The period of the divider’s output is continuously modulated with accuracy of a single (or several) VCO periods. Δ Σ order determines the number of division factors used, i.e., with how many different VCO periods is the divider’s output period modulated.
- 3.
Note that the loop settles to a condition where Φe is a zero-mean signal, i.e., where ΦREF = ΦDIV.
- 4.
The improvement is somewhat limited since for higher gain G CP, the CP current must increase which also leads to a higher local noise generation of the CP.
- 5.
Valid for small signal approximation of a sinusoid around zero.
- 6.
Maybe the best proof for the potential this system has is in today’s frequency synthesis state of the art. The current record holders in PLL FOM, presented at ISSCC 2018, are two (sub)sampling PLLs [Sharkia18, Sharma18]. Moreover, the subsampling architecture has been successfully and widely applied for high-performance integer-N LO synthesis since its introduction, in digitally intensive configurations [Ru13], ring-oscillator-based [Sogo12] loops, at millimeter frequencies [Szortyka14], and in automotive radar systems [Yi13].
References
J. Borremans, K. Vengattaramane, V. Giannini, B. Debaillie, W. Van Thillo, J. Craninckx, A 86 MHz–12 GHz digital-intensive PLL for software-defined radios, using a 6 fJ/step TDC in 40 nm digital CMOS. IEEE J. Solid-State Circuits 45(10), 2116–2129 (2010)
J. Craninckx, M.S. Steyaert, A fully integrated CMOS DCS-1800 frequency synthesizer. IEEE J. Solid-State Circuits 33(12), 2054–2065 (1998)
J. Craninckx, M. Steyaert, Wireless CMOS Frequency Synthesizer Design (Kluwer Academic Publishers, Dordrecht, 1998)
X. Gao, E. Klumperink, M. Bohsali, B. Nauta, A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N 2 . IEEE J. Solid-State Circuits 44(12), 3253–3263 (2009)
X. Gao, E. Klumperink, G. Socci, M. Bohsali, B. Nauta, Spur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector. IEEE J. Solid-State Circuits 45(9), 1809–1821 (2010)
F.M. Gardner, Phaselock Techniques (Wiley, London, 1966)
M. Gupta, B.-S. Song, A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration. IEEE J. Solid-State Circuits 41(12), 2842–2851 (2006)
C.-M. Hsu, M.Z. Straayer, M.H. Perrott, A low-noise wide-BW 3.6-GHz digital Δ Σ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation. IEEE J. Solid-State Circuits 43(12), 2776–2786 (2008)
H. Huh, Y. Koo, K.-Y. Lee, Y. Ok, S. Lee, D. Kwon, J. Lee, J. Park, K. Lee, D.-K. Jeong et al., A CMOS dual-band fractional-N synthesizer with reference doubler and compensated charge pump, in 2004 IEEE International Solid-State Circuits Conference, Digest of Technical Papers. ISSCC (IEEE, Piscataway, 2004), pp. 100–516
H.S. Kim, C. Ornelas, K. Chandrashekar, D. Shi, P.-E. Su, P. Madoglio, W.Y. Li, A. Ravi, A digital fractional-N PLL with a PVT and mismatch insensitive TDC utilizing equivalent time sampling technique. IEEE J. Solid-State Circuits 48(7), 1721–1729 (2013)
A.L. Lacaita, S. Levantino, C. Samori, Integrated Frequency Synthesizers for Wireless Systems (Cambridge University Press, Cambridge, 2007)
S. Meninger, M. Perrott, Low Phase noise, High bandwidth frequency synthesizer techniques, Ph.D. dissertation, Massachusetts Institute of Technology, 2005
S.E. Meninger, M.H. Perrott, A 1-MHZ bandwidth 3.6-GHz 0.18-um CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise. IEEE J. Solid-State Circuits 41(4), 966–980 (2006)
S. Pamarti, L. Jansson, I. Galton, A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation. IEEE J. Solid-State Circuits 39(1), 49–62 (2004)
B. Razavi, A study of phase noise in CMOS oscillators. IEEE J. Solid-State Circuits 31(3), 331–343 (1996)
B. Razavi, R. Behzad, RF Microelectronics, vol. 2 (Prentice Hall, New Jersey, 1998)
T.A. Riley, M.A. Copeland, T.A. Kwasniewski, Delta-sigma modulation in fractional-N frequency synthesis. IEEE J. Solid-State Circuits 28(5), 553–559 (1993)
Z. Ru, P. Geraedts, E. Klumperink, X. He, B. Nauta, A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO, in 2013 Symposium on VLSI Circuits (VLSIC) (IEEE, Piscataway, 2013), pp. C194–C195
R.B. Sepe, Frequency multiplier and frequency waveform generator, U.S. Patent 3,551,826, 29 Dec 1970
A. Sharkia, S. Mirabbasi, S. Shekhar, A 0.01 mm2 4.6-to-5.6GHz sub-sampling type-I frequency synthesizer with -254dB FOM, in 2018 IEEE International Solid-State Circuits Conference (ISSCC) (IEEE, Piscataway, 2018), pp. 256–257
J. Sharma, H. Krishnaswamy, A dividerless reference-sampling RF PLL with -253.5dB jitter FOM and <-67dBc reference spurs, in 2018 IEEE International Solid-State Circuits Conference (ISSCC) (IEEE, Piscataway, 2018), pp. 257–258
K. Sogo, A. Toya, T. Kikkawa, A ring-VCO-based sub-sampling PLL CMOS circuit with -119 dBc/Hz phase noise and 0.73 ps jitter, in 2012 Proceedings of the ESSCIRC (ESSCIRC) (IEEE, Piscataway, 2012), pp. 253–256
R.B. Staszewski, P.T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS (Wiley, London, 2006)
R.B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J.L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung et al., All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS. IEEE J. Solid-State Circuits 39(12), 2278–2291 (2004)
J.T. Stauth, Energy Efficient Wireless Transmitters: Polar and Direct-Digital Modulation Architectures (ProQuest, Ann Arbor, 2008)
M.A. Straayer, Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators. Ph.D. dissertation, Massachusetts Institute of Technology, 2008
V. Szortyka, Q. Shi, K. Raczkowski, B. Parvais, M. Kuijk, P. Wambacq, 21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS, in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (IEEE, Piscataway, 2014), pp. 366–367
E. Temporiti, C. Weltin-Wu, D. Baldi, M. Cusmai, F. Svelto, A 3.5 GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation. IEEE J. Solid-State Circuits 45(12), 2723–2736 (2010)
K. Vengattaramane, J. Borremans, M. Steyaert, J. Craninckx, A gated ring oscillator based parallel-TDC system with digital resolution enhancement, in IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 (IEEE, Piscataway, 2009), pp. 57–60
C.-W. Yao, A.N. Willson, A 2.8–3.2-GHz fractional-N digital PLL with ADC-assisted TDC and inductively coupled fine-tuning DCO. IEEE J. Solid-State Circuits 48(3), 698–710 (2013)
X. Yi, C.C. Boon, J. Sun, N. Huang, W.M. Lim, A low phase noise 24/77 GHz dual-band sub-sampling PLL for automotive radar applications in 65 nm CMOS technology, in 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) (IEEE, Piscataway, 2013), pp. 417–420
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Markulic, N., Raczkowski, K., Craninckx, J., Wambacq, P. (2019). Introduction. In: Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-030-10958-5_1
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DOI: https://doi.org/10.1007/978-3-030-10958-5_1
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