Abstract
Today’s switches and routers require high-speed and large-capacity packet buffers to guarantee a line rate up to 100 Gbps as well as more fine-grained quality of service. For this, this paper proposes an efficient parallel hybrid SRAM/DRAM architecture for high-bandwidth switches and routers. Tail SRAM and head SRAM are used for guaranteeing the middle DRAMs are accessed in a larger granularity to improve the bandwidth utilization. Then, a simple yet efficient memory management algorithm is designed. The memory space is dynamically allocated when a flow arrives, and a hard timeout is assigned for each queue. Hence, the SRAM space is utilized more efficiently. A queueing system is used to model the proposed method, and theoretical analysis is performed to optimize the timeout value. Simulation shows that the proposed architecture can reduce packet loss rate significantly compared with previous solutions with the same SRAM capacity.
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Acknowledgements
This work was supported in part by the project of Science and Technology on Information Transmission and Dissemination in Communication Networks Laboratory (KX152600010/ITD-U15001), the National Natural Science Foundation of China (61502204, 61306047), the Fundamental Research Funds for the Central Universities (JB140112), and the Qing Lan Project of Jiangsu.
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© 2019 ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
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Zheng, L., Qiu, Z., Pan, W., Gao, Y. (2019). A High-Speed Large-Capacity Packet Buffer Scheme for High-Bandwidth Switches and Routers. In: Liu, X., Cheng, D., Jinfeng, L. (eds) Communications and Networking. ChinaCom 2018. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 262. Springer, Cham. https://doi.org/10.1007/978-3-030-06161-6_37
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DOI: https://doi.org/10.1007/978-3-030-06161-6_37
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