Conflict-Free Block-with-Stride Access of 2D Storage Structure
Parallel memory modules can be used to increase memory bandwidth and feed a processor with the required access patterns of data. The parallel storage mechanism organized and managed by multiple storage modules can suit applications of images and videos. Previous investigation into data storage schemes can be used to achieve continuous conflict free access by rows, columns or blocks, however it is not only satisfied with some sliding window applications in video and image processing algorithms (including convolutional neural networks, sub-pixel difference, 2D filtering, etc.) which need non-conflicting access by steps in computation, but also there is a different demand for horizontal and vertical strides in computing sub-processes. This paper presents a storage scheme that support for row access without collision alignment, and non-aligned block-with-stride access storage modes beginning at any address. Theoretical proofs and experiments verify the correct ness of the module address (module number to which the address is mapped). And in hardware design, it was found that in the typical case there was no path violation and with less area overhead. It suitable for application of CNN to improve performance in algorithm in convolutional.
KeywordsMain memory architectures 2D memory conflicts Parallel storage scheme
- 1.Chen, S., Postula, A., Jozwiak, L.: Synthesis of XOR storage schemes with different cost for minimization of memory contention. In: 1999 Proceedings of the Euromicro Conference, vol. 1, pp. 170–177. IEEE (1999)Google Scholar
- 3.Aho, E., Vanne, J., Kuusilinna, K., et al.: Address computation in configurable parallel memory architecture. IEICE Trans. Inf. Syst. 87-D(7), 1674–1681 (2004)Google Scholar
- 4.Takala, J., Jarvinen, T.: Stride permutation access in interleaved memory systems (2003)Google Scholar
- 8.Park, J.W.: Conflict-free memory system and method of address calculation and data routing by using the same. US 6845423 B2[P], US (2005)Google Scholar
- 10.Liu, C., Yan, X., Qin, X.: An optimized linear skewing interleave scheme for on-chip multi-access memory systems. In: ACM Great Lakes Symposium on VLSI, pp. 8–13. ACM (2007)Google Scholar