Exploiting the Table of Energy and Power Leverages

  • Issam Raïs
  • Laurent LefèvreEmail author
  • Anne-Cécile Orgerie
  • Anne Benoit
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11336)


Large scale distributed systems and supercomputers consume huge amounts of energy. To address this issue, a large set of hardware and software capabilities and techniques (leverages) exist to modify power and energy consumption in large scale systems. Discovering, benchmarking and efficiently exploiting such leverages, remains a real challenge for most of the users. In this paper, we define leverages and the table of leverages, and we propose algorithms and predicates that ease the reading of the table of leverages and extract knowledge from it.


  1. 1.
    Acar, H., Alptekin, G.I., Gelas, J.-P., Ghodous, P.: Towards a green and sustainable software. In: Concurrent Engineering, pp. 471–480 (2015)Google Scholar
  2. 2.
    International Energy Agency. Digitalization & Energy. White paper (2017)Google Scholar
  3. 3.
    Balouek, D., et al.: Adding virtualization capabilities to the Grid’5000 testbed. In: Ivanov, I.I., van Sinderen, M., Leymann, F., Shan, T. (eds.) CLOSER 2012. CCIS, vol. 367, pp. 3–20. Springer, Cham (2013). Scholar
  4. 4.
    Chetsa, G.L.T.E.A.: A user friendly phase detection methodology for hpc systems’ analysis. In: IEEE International Conference on and IEEE Cyber, Physical and Social Computing (2013)Google Scholar
  5. 5.
    Dagum, L., Menon, R.: OpenMP: an industry standard API for shared-memory programming. IEEE Comput. Sci. Eng. 5, 46–55 (1998)CrossRefGoogle Scholar
  6. 6.
    Gallas, B., Verma, V.: Embedded Pentium (R) processor system design for Windows CE, Wescon/98, pp. 114–123. IEEE (1998)Google Scholar
  7. 7.
    Georgiou, Y., Glesser, D., Rzadca, K., Trystram, D.: A scheduler-level incentive mechanism for energy efficiency in HPC. In: CCGrid, pp. 617–626 (2015)Google Scholar
  8. 8.
    Lomont, C.: Introduction to intel advanced vector extensions. Intel White Paper, pp. 1–21 (2011)Google Scholar
  9. 9.
    Peleg, A., Weiser, U.: MMX technology extension to the Intel architecture. IEEE Micro 16(4), 42–50 (1996)CrossRefGoogle Scholar
  10. 10.
    Raïs, I., Orgerie, A.-C., Quinson, M.: Impact of shutdown techniques for energy-efficient cloud data centers. In: Carretero, J., Garcia-Blas, J., Ko, R.K.L., Mueller, P., Nakano, K. (eds.) ICA3PP 2016. LNCS, vol. 10048, pp. 203–210. Springer, Cham (2016). Scholar
  11. 11.
    Suleiman, D., Ibrahim, M., Hamarash, I.: Dynamic voltage frequency scaling (DVFS) for microprocessors power and energy reduction. In: International Conference on Electrical and Electronics Engineering (2005)Google Scholar

Copyright information

© Springer Nature Switzerland AG 2018

Authors and Affiliations

  • Issam Raïs
    • 1
  • Laurent Lefèvre
    • 1
    Email author
  • Anne-Cécile Orgerie
    • 3
  • Anne Benoit
    • 1
    • 2
  1. 1.Laboratoire LIPÉcole Normale Supérieure de Lyon & InriaLyonFrance
  2. 2.Georgia Institute of TechnologyAtlantaUSA
  3. 3.Univ. Rennes, Inria, CNRS, IRISARennesFrance

Personalised recommendations