Machine Learning-Based Aging Analysis

  • Arunkumar VijayanEmail author
  • Krishnendu Chakrabarty
  • Mehdi B. Tahoori


Bias temperature instability (BTI)-induced transistor aging, one of the major reliability threats in nanoscale VLSI, degrades path delay over time and may lead to timing failures. Runtime solutions based on online monitoring and adaptation are required for resilience in nanoscale integrated circuits, as design-time solutions and guard bands are no longer sufficient. Chip health monitoring is, therefore, necessary to track delay changes on a per-chip basis over the chip lifetime operation. However, direct monitoring based on actual measurement of path delays can only track a coarse-grained aging trend in a reactive manner, not suitable for proactive fine-grain adaptations. We propose a low-cost and fine-grained workload-induced stress monitoring approach, based on machine learning techniques, to accurately predict aging-induced delay. We integrate space and time sampling of selective flip-flops into the runtime monitoring infrastructure in order to reduce the cost of monitoring the workload. The prediction model is trained offline using support-vector regression and implemented in software. This approach can leverage proactive adaptation techniques to mitigate further aging of the circuit by monitoring aging trends. Simulation results for realistic open-source benchmark circuits highlight the accuracy of the proposed approach.


  1. 1.
    M. Agarwal, B.C. Paul, M. Zhang, S. Mitra, Circuit failure prediction and its application to transistor aging, in IEEE VLSI Test Symposium (2007), pp. 277–286Google Scholar
  2. 2.
    J. Benesty, J. Chen, Y. Huang, I. Cohen, Pearson correlation coefficient, in Noise Reduction in Speech Processing (Springer, Berlin, 2009), pp. 1–4Google Scholar
  3. 3.
    S. Borkar, Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro 25(6), 10–16 (2005)CrossRefGoogle Scholar
  4. 4.
    K. Bowman et al., Circuit techniques for dynamic variation tolerance, in ACM/IEEE Design Automation Conference (2009), pp. 4–7Google Scholar
  5. 5.
    T.-B. Chan, J. Sartori, P. Gupta, R. Kumar, On the efficacy of NBTI mitigation techniques, in Design, Automation and Test in Europe Conference and Exhibition (IEEE, Piscataway, 2011), pp. 1–6Google Scholar
  6. 6.
    B. Choi, Y. Shin, Lookup table-based adaptive body biasing of multiple macros, in International Symposium on Quality Electronic Design (2007), pp. 533–538Google Scholar
  7. 7.
    S. Corbetta, W. Fornaciari, NBTI mitigation in microprocessor designs, in Proceedings of the Great Lakes Symposium on VLSI (ACM, New York, 2012)Google Scholar
  8. 8.
    C. Cortes, V. Vapnik, Support-vector networks. Mach. Learn. 20(3), 273–297 (1995)zbMATHGoogle Scholar
  9. 9.
    D. Ernst, N.S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, T. Mudge, Razor: a low-power pipeline based on circuit-level timing speculation, in IEEE/ACM International Symposium on Microarchitecture (2003), pp. 7–18Google Scholar
  10. 10.
    F. Firouzi, F. Ye, K. Chakrabarty, M.B. Tahoori, Aging- and variation-aware delay monitoring using representative critical path selection. ACM Trans. Des. Autom. Electron. Syst. 20(3), 39 (2015)Google Scholar
  11. 11.
    T. Fischer, J. Desai, B. Doyle, S. Naffziger, B. Patella, A 90-nm variable frequency clock system for a power-managed itanium architecture processor. J. Solid-State Circuits 41(1), 218–228 (2006)CrossRefGoogle Scholar
  12. 12.
    M. Floyd, M. Allen-Ware, K. Rajamani, B. Brock, C. Lefurgy, A.J. Drake, L. Pesantez, T. Gloekler, J.A. Tierno, P. Bose, A. Buyuktosunoglu, Introducing the adaptive energy management features of the POWER7 chip. IEEE/ACM Int. Symp. Microarchitecture 31(2), 60–75 (2011)Google Scholar
  13. 13.
    M. Fojtik, D. Fick, Y. Kim, N. Pinckney, D. Harris, D. Blaauw, D. Sylvester, Bubble razor: an architecture-independent approach to timing-error detection and correction, in IEEE International Solid-State Circuits Conference Digest of Technical Papers (IEEE, Piscataway, 2012), pp. 488–490Google Scholar
  14. 14.
    G. Gammie, A. Wang, M. Chau, S. Gururajarao, R. Pitts, F. Jumel, S. Engel, P. Royannez, R. Lagerquist, H. Mair, J. Vaccani, G. Baldwin, K. Heragu, R. Mandal, M. Clinton, D. Arden, U. Ko, A 45 nm 3.5G baseband-and-multimedia application processor using adaptive body-bias and ultra-low-power techniques, in International Solid-State Circuits Conference (2008), pp. 258–611Google Scholar
  15. 15.
    B. Guenin, K.C. Gross, A. Gribok, A. Urmanov, A new sensor validation technique for the enhanced RAS of high end servers, in International Conference on Machine Learning: Models, Technologies and Applications (2004)Google Scholar
  16. 16.
    S. Gupta, S.S. Sapatnekar, Employing circadian rhythms to enhance power and reliability. ACM Trans. Des. Autom. Electron. Syst. 18(3), 38 (2013)Google Scholar
  17. 17.
    S. Gupta, S.S. Sapatnekar, Variation-aware variable latency design. IEEE Trans. Very Large Scale Integration Syst. 22(5), 1106–1117 (2014)CrossRefGoogle Scholar
  18. 18.
    A.K. Jain, Data clustering: 50 years beyond K-means. Pattern Recogn. Lett. 31(8), 651–666 (2010)CrossRefGoogle Scholar
  19. 19.
    A. Jain, D. Zongker, Feature selection: evaluation, application, and small sample performance. IEEE Trans. Pattern Anal. Mach. Intell. 19(2), 153–158 (1997)CrossRefGoogle Scholar
  20. 20.
    K. Kang, H. Kufluoglu, M.A. Alam, K. Roy, Efficient transistor-level sizing technique under temporal performance degradation due to NBTI, in IEEE International Conference on Computer Design (2007), pp. 216–221Google Scholar
  21. 21.
    K. Kang, S.P. Park, K. Roy, M.A. Alam, Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance, in International Conference on Computer-Aided Design (2007)Google Scholar
  22. 22.
    B. Kapoor, S. Hemmady, S. Verma, K. Roy, M.A. D’Abreu, Impact of SoC power management techniques on verification and testing, in International Symposium on Quality Electronic Design (2009), pp. 692–695Google Scholar
  23. 23.
    E. Karl, D. Blaauw, D. Sylvester, T. Mudge, Multi-mechanism reliability modeling and management in dynamic systems. Trans. VLSI Syst. 16(4), 476–487 (2008)CrossRefGoogle Scholar
  24. 24.
    J. Keane, X. Wang, D. Persaud, C.H. Kim, An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB. IEEE J. Solid-State Circuits 45(4), 817–829 (2010)CrossRefGoogle Scholar
  25. 25.
    S.V. Kumar, C.H. Kim, S.S. Sapatnekar, NBTI-aware synthesis of digital circuits, in ACM/IEEE Design Automation Conference (2007), pp. 370–375Google Scholar
  26. 26.
    D. Lorenz, G. Georgakos, U. Schlichtmann, Aging analysis of circuit timing considering NBTI and HCI, in IEEE International On-Line Testing Symposium (2009), pp. 3–8Google Scholar
  27. 27.
    H. Mair, A. Wang, G. Gammie, D. Scott, P. Royannez, S. Gururajarao, M. Chau, R. Lagerquist, L. Ho, M. Basude, N. Culp, A. Sadate, D. Wilson, F. Dahan, J. Song, B. Carlson, U. Ko, A 65-nm mobile multimedia applications processor with an adaptive power management scheme to compensate for variations, in IEEE Symposium on VLSI Circuits (2007)Google Scholar
  28. 28.
    J.W. McPherson, Reliability challenges for 45 nm and beyond, in ACM/IEEE Design Automation Conference (2006), pp. 176–181Google Scholar
  29. 29.
    E. Mintarno, J. Skaf, R. Zheng, J. Velamala, Y. Cao, S. Boyd, R.W. Dutton, S. Mitra, Optimized self-tuning for circuit aging, in Design, Automation and Test in Europe Conference and Exhibition (2010), pp. 586–591Google Scholar
  30. 30.
    E. Mintarno, J. Skaf, R. Zheng, J.B. Velamala, Y. Cao, S. Boyd, R.W. Dutton, S. Mitra, Self-tuning for maximized lifetime energy-efficiency in the presence of circuit aging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5), 760–773 (2011)CrossRefGoogle Scholar
  31. 31.
    H. Mostafa, M. Anis, M. Elmasry, Adaptive body bias for reducing the impacts of NBTI and process variations on 6T SRAM cells. IEEE Trans. Circuits Syst. 58(12), 2859–2871 (2011)MathSciNetCrossRefGoogle Scholar
  32. 32.
    Nangate 45 nm open cell library v1.3.
  33. 33.
    B.C. Paul, K. Kang, H. Kufluoglu, M.A. Alam, K. Roy, Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits, in Design, Automation and Test in Europe Conference and Exhibition (2006), pp. 780–785Google Scholar
  34. 34.
    F. Pedregosa, G. Varoquaux, A. Gramfort, V. Michel, B. Thirion, O. Grisel, M. Blondel, P. Prettenhofer, R. Weiss, V. Dubourg et al., Scikit-learn: machine learning in python. J. Mach. Learn. Res. 12, 2825–2830 (2011)MathSciNetzbMATHGoogle Scholar
  35. 35.
    D. Pelleg, A. Moore, Accelerating exact K-means algorithms with geometric reasoning, in ACM International Conference on Knowledge Discovery and Data Mining (1999), pp. 277–281Google Scholar
  36. 36.
    C. Poirier, R. McGowen, C. Bostak, S. Naffziger, Power and temperature control on a 90-nm itanium family processor. J. Solid-State Circuits 41(1), 229–237 (2006)CrossRefGoogle Scholar
  37. 37.
    N. Shah, R. Samanta, M. Zhang, J. Hu, D. Walker, Built-in proactive tuning system for circuit aging resilience, in IEEE Defect and Fault Tolerance in VLSI Systems (2008), pp. 96–104Google Scholar
  38. 38.
    J. Srinivasan, S.V. Adve, P. Bose, J.A. Rivers, The case for lifetime reliability-aware microprocessors, in ACM International Symposium on Computer architecture, vol. 32 (2004), p. 276Google Scholar
  39. 39.
    J. Srinivasan, S.V. Adve, P. Bose, J.A. Rivers, Lifetime reliability: toward an architectural solution. IEEE Micro 25, 70–80 (2005)CrossRefGoogle Scholar
  40. 40.
    J. Srinivasan, S.V. Adve, P. Bose, J.A. Rivers, Exploiting structural duplication for lifetime reliability enhancement, in ACM International Symposium on Computer architecture, June 2005, pp. 520–531Google Scholar
  41. 41.
    K. Sutaria, A. Ramkumar, R. Zhu, R. Rajveev, Y. Ma, Y. Cao, BTI-induced aging under random stress waveforms: modeling, simulation and silicon validation, in Design Automation Conference (DAC) (2014), pp. 1–6Google Scholar
  42. 42.
    D. Sylvester, D. Blaauw, E. Karl, Elastic: an adaptive self-healing architecture for unpredictable silicon. Des. Test 23(6), 484–490 (2006)Google Scholar
  43. 43.
    A. Tiwari, J. Torrellas, Facelift: hiding and slowing down aging in multicores, in 2008 41st IEEE/ACM International Symposium on Microarchitecture (2008)Google Scholar
  44. 44.
    J.W. Tschanz, J.T. Kao, S.G. Narendra, R. Nair, D.A. Antoniadis, A.P. Chandrakasan, V. De, Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. J. Solid-State Circuits 37(11), 1396–1402 (2002)CrossRefGoogle Scholar
  45. 45.
    J. Tschanz, N.S. Kim, S. Dighe, J. Howard, G. Ruhl, S. Vangal, S. Narendra, Y. Hoskote, H. Wilson, C. Lam, M. Shuman, C. Tokunaga, D. Somasekhar, S. Tang, D. Finan, T. Karnik, N. Borkar, N. Kurd, V. De, Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging, in International Solid-State Circuits Conference (2007), pp. 292–604Google Scholar
  46. 46.
    S. Wang, J. Chen, M. Tehranipoor, Representative critical reliability paths for low-cost and accurate on-chip aging evaluation, in IEEE/ACM International Conference on Computer-Aided Design (2012), pp. 736–741Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Arunkumar Vijayan
    • 1
    Email author
  • Krishnendu Chakrabarty
    • 2
  • Mehdi B. Tahoori
    • 1
  1. 1.Karlsruhe Institute of TechnologyKarlsruheGermany
  2. 2.Duke UniversityDurhamUSA

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