Fast Statistical Analysis of Rare Circuit Failure Events

  • Jun TaoEmail author
  • Shupeng Sun
  • Xin LiEmail author
  • Hongzhou Liu
  • Kangsheng Luo
  • Ben Gu
  • Xuan ZengEmail author


Accurately estimating the rare failure rates for nanoscale memory circuits is a challenging task, especially when the variation space is high-dimensional. In this chapter, we summarize two novel techniques to address this technical challenge. First, we describe a subset simulation (SUS) technique to estimate the rare failure rates for continuous performance metrics. The key idea of SUS is to express the rare failure probability of a given circuit as the product of several large conditional probabilities by introducing a number of intermediate failure events. These conditional probabilities can be efficiently estimated with a set of Markov chain Monte Carlo samples generated by a modified Metropolis algorithm. Second, to efficiently estimate the rare failure rates for discrete performance metrics, scaled-sigma sampling (SSS) can be used. SSS aims to generate random samples from a distorted probability distribution for which the standard deviation (i.e., sigma) is scaled up. Next, the failure rate is accurately estimated from these scaled random samples by using an analytical model derived from the theorem of “soft maximum”. Our experimental results of several nanoscale circuit examples demonstrate that SUS and SSS achieve significantly improved accuracy over other traditional techniques when the dimensionality of the variation space is more than a few hundred.


  1. 1.
    S. Au, J. Beck, Estimation of small failure probabilities in high dimensions by subset simulation. Probab. Eng. Mech. 16(4), 263–277 (2001)CrossRefGoogle Scholar
  2. 2.
    A. Bhavnagarwala, X. Tang, J. Meindl, The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J. Solid-State Circuits 36(4), 658–665 (2001)CrossRefGoogle Scholar
  3. 3.
    C. Bishop, Pattern Recognition and Machine Learning (Prentice Hall, Upper Saddle River, 2007)Google Scholar
  4. 4.
    S. Boyd, L. Vandenberghe, Convex Optimization (Cambridge University Press, Cambridge, 2009)zbMATHGoogle Scholar
  5. 5.
    B. Calhoun, Y. Cao, X. Li, K. Mai, L. Pileggi, R. Rutenbar, K. Shepard, Digital circuit design challenges and opportunities in the era of nanoscale CMOS. Proc. IEEE 96(2), 343–365 (2008)CrossRefGoogle Scholar
  6. 6.
    F. Cérou, P. Moral, T. Furon, A. Guyader, Sequential Monte Carlo for rare event estimation. Stat. Comput. 22(3), 795–808 (2012)MathSciNetCrossRefGoogle Scholar
  7. 7.
    L. Dolecek, M. Qazi, D. Shah, A. Chandrakasan, Breaking the simulation barrier: SRAM evaluation through norm minimization, in International Conference on Computer-Aided Design (2008), pp. 322–329Google Scholar
  8. 8.
    B. Efron, R. Tibshirnani, An Introduction to the Bootstrap (Chapman & Hall/CRC, London, 1993)CrossRefGoogle Scholar
  9. 9.
    R. Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine, A statistical simulation method for reliability analysis of SRAM core-cells, in Design Automation Conference (2010), pp. 853–856Google Scholar
  10. 10.
    C. Gu, J. Roychowdhury, An efficient, fully nonlinear, variability aware non-Monte-Carlo yield estimation procedure with applications to SRAM cells and ring oscillators, in IEEE Asia and South Pacific Design Automation Conference (2008), pp. 754–761Google Scholar
  11. 11.
    A. Guyader, N. Hengartner, E. Matzner-Løber, Simulation and estimation of extreme quantiles and extreme probabilities. Appl. Math. Optim. 64(2), 171–196 (2011)MathSciNetCrossRefGoogle Scholar
  12. 12.
    R. Heald, P. Wang, Variability in sub-100nm SRAM designs, in International Conference on Computer-Aided Design (2004), pp. 347–352Google Scholar
  13. 13.
    R. Kanj, R. Joshi, S. Nassif, Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events, in Design Automation Conference (2006), pp. 69–72Google Scholar
  14. 14.
    R. Kanj, R. Joshi, Z. Li, J. Hayes, S. Nassif, Yield estimation via multi-cones, in Design Automation Conference (2012), pp. 1107–1112Google Scholar
  15. 15.
    K. Katayama, S. Hagiwara, H. Tsutsui, H. Ochi, T. Sato, Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis, in International Conference on Computer-Aided Design (2010), pp. 703–708Google Scholar
  16. 16.
    A. Papoulis, S. Pillai, Probability, Random Variables and Stochastic Process (McGraw-Hill, New York, 2001)Google Scholar
  17. 17.
    M. Qazi, M. Tikekar, L. Dolecek, D. Shah, A. Chandrakasan, Loop flattening and spherical sampling: highly efficient model reduction techniques for SRAM yield analysis, in Design, Automation & Test in Europe (2010), pp. 801–806Google Scholar
  18. 18.
    A. Singhee, R. Rutenbar, Statistical blockade: very fast statistical simulation and modeling of rare circuit events, and its application to memory design. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 28(8), 1176–1189 (2009)CrossRefGoogle Scholar
  19. 19.
    S. Sun, X. Li, Fast statistical analysis of rare circuit failure events via subset simulation in high-dimensional variation space, in International Conference on Computer-Aided Design (2014), pp. 324–331Google Scholar
  20. 20.
    S. Sun, Y. Feng, C. Dong, X. Li, Efficient SRAM failure rate prediction via Gibbs sampling. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 31(12), 1831–1844 (2012)CrossRefGoogle Scholar
  21. 21.
    S. Sun, X. Li, H. Liu, K. Luo, B. Gu, Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space, in International Conference on Computer-Aided Design (2013), pp. 478–485Google Scholar
  22. 22.
    R. Topaloglu, Early, accurate and fast yield estimation through Monte Carlo-alternative probabilistic behavioral analog system simulations, in IEEE VLSI Test Symposium (2006), pp. 137–142Google Scholar
  23. 23.
    J. Wang, S. Yaldiz, X. Li, L. Pileggi, SRAM parametric failure analysis, in Design Automation Conference (2009), pp. 496–501Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.State Key Laboratory of ASIC and System, School of MicroelectronicsFudan UniversityShanghaiChina
  2. 2.Department of Electrical and Computer EngineeringCarnegie Mellon UniversityPittsburghUSA
  3. 3.Department of Electrical and Computer EngineeringDuke UniversityDurhamUSA
  4. 4.Cadence Design Systems, Inc.PittsburghUSA
  5. 5.Cadence Design Systems, Inc.AustinUSA

Personalised recommendations