Skip to main content

Abstract

Fault injection is a widely used method to evaluate fault effects and error mitigation in a design. While not a replacement for standard Radiation-Hardness Assurance methodologies, it can provide valuable information in a quick and inexpensive manner. Moreover, recent developments have improved performance by several orders of magnitude, thus enabling the realization of extremely large fault injection campaigns. Today, fault injection can be used to forecast the expected circuit behaviour in the occurrence of SEUs and SETs, validate error mitigation approaches and detect weak areas that require error mitigation. This chapter will review the most relevant fault injection methods, covering software-based techniques, simulation techniques and FPGA-based emulation techniques. Recent advances for SET and MCU emulation are presented.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. R.C. Baumann, Radiation-induced soft errors in advanced semiconductor technologies. IEEE Trans. Device Mater. Reliab. 5(3), 305–316 (2005)

    Article  Google Scholar 

  2. H. Ziade et al., A survey on fault injection techniques. Int. Arab J. Inf. Technol. 1(2), 171–186 (2004)

    Google Scholar 

  3. M.C. Hsueh, T.K. Tsai, R.K. Iyer, Fault injection techniques and tools. Computer 30(4), 75–82 (1997)

    Article  Google Scholar 

  4. H.M. Quinn, D.A. Black, W.H. Robinson, S.P. Buchner, Fault simulation and emulation tools to augment radiation-hardness assurance testing. IEEE Trans. Nucl. Sci. 60(3), 2119–2142 (2013)

    Article  Google Scholar 

  5. R. Velazco, S. Karoui, T. Chapuis, D. Benezech, L.H. Rosier, Heavy ion test results for the 68020 microprocessor and the 68882 coprocessor. IEEE Trans. Nucl. Sci. 39(3), 436–440 (1992)

    Article  Google Scholar 

  6. R. Velazco, T. Calin, M. Nicolaidis, S.C. Moss, S.D. LaLumondiere, V.T. Tran, R. Koga, SEU-hardened storage cell validation using a pulsed laser. IEEE Trans. Nucl. Sci. 43(6), 2843–2848 (1996)

    Article  Google Scholar 

  7. F. Vargas, D.L. Cavalcante, E. Gatti, D. Prestes, D. Lupi, On the proposition of an EMI-based fault injection approach, in 11th IEEE International On-Line Testing Symposium, (Saint Raphaël, French Riviera, 2005), pp. 207–208

    Chapter  Google Scholar 

  8. J. Arlat, Y. Crouzet, J. Karlsson, P. Folkesson, E. Fuchs, G.H. Leber, Comparison of physical and software-implemented fault injection techniques. IEEE Trans. Comput. 52(9), 1115–1133 (2003)

    Article  Google Scholar 

  9. R. Velazco, S. Rezgui, R. Ecoffet, Predicting error rate for microprocessor-based digital architectures through C.E.U. (code emulating upsets) injection. IEEE Trans. Nucl. Sci. 47(6), 2405–2411 (2000)

    Article  Google Scholar 

  10. J. Aidemark, J. Vinter, P. Folkesson, J. Karlsson, GOOFI: Generic Object-Oriented Fault Injection Tool, in Proceedings of the International Conference on Dependable Systems and Networks (DSN'2001), July 2001

    Google Scholar 

  11. M. Portela-Garcia, C. Lopez-Ongil, M. Garcia Valderas, L. Entrena, Fault injection in modern microprocessors using on-Chip debugging infrastructures. IEEE Trans. Depend. Sec. Comput. 8(2), 308–314 (2011)

    Article  Google Scholar 

  12. M. Alderighi, F. Casini, S. D’Angelo, M. Mancini, S. Pastore, G.R. Sechi, R. Weigand, Evaluation of single event upset mitigation schemes for SRAM based FPGAs using the FLIPPER fault injection platform, in Proceedings of 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 105–113, Sep. 2007

    Google Scholar 

  13. Soft Error Mitigation Controller V4.1 Product Guide, Xilinx Inc., White Paper PG036, Nov. 2014

    Google Scholar 

  14. L. Berrojo, F. Corno, L. Entrena, I. González, C. López, M. Sonza, G. Squillero, An industrial environment for high-level fault-tolerant structures insertion and validation, in IEEE VLSI test symposium, Monterrey, CA, May 2002

    Google Scholar 

  15. D. Gonzalez-Gutierrez, Single event upsets simulation tool functional description, ESA Report TEC-EDM/DCC-SST2, July 2004

    Google Scholar 

  16. M.G. Valderas, M.P. Garcia, R.F. Cardenal, C.L. Ongil, L. Entrena, Advanced simulation and emulation techniques for fault injection, in IEEE International Symposium on Industrial Electronics, pp. 3339–3344, 2007

    Google Scholar 

  17. L. Antoni, R. Leveugle, B. Feher, Using run-time reconfiguration for fault injection in HW prototypes, in IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 245–253, 2002

    Google Scholar 

  18. M.A. Aguirre, J.N. Tombs, V. Baena, F. Muñoz-Chavero, A. Torralba, A. Fernandez-Leon, F. Tortosa, FT-UNSHADES: a new system for SEU injection, analysis and diagnostics over post synthesis netlist, in Proceedings of the NASA Military and Aerospace Programmable Logic Devices (MAPLD), Sep. 2005

    Google Scholar 

  19. J.M. Mogollon, H. Guzmán-Miranda, J. Nápoles, J. Barrientos, M.A. Aguirre, FTUNSHADES2: A novel platform for early evaluation of robustness against SEE, in 12th European Conference on Radiation and its Effects on Components and Systems, pp. 169–174, 2011

    Google Scholar 

  20. P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante, Exploiting circuit emulation for fast hardness evaluation. IEEE Trans. Nucl. Sci. 48(6), 2210–2216 (2001)

    Article  Google Scholar 

  21. C. López-Ongil, M. García-Valderas, M. Portela-García, L. Entrena, Autonomous fault emulation: a new FPGA-based acceleration system for hardness evaluation. IEEE Trans. Nucl. Sci. 54(1), 252–261 (2007)

    Article  Google Scholar 

  22. D. Alexandrescu, L. Anghel, M. Nicolaidis, Simulating single event transients in VDSM ICs for ground level radiation. J. Electron. Test. 20(4), 413–421 (2004)

    Article  Google Scholar 

  23. E. Costenaro, D. Alexandrescu, K. Belhaddad, M. Nicolaidis, A practical approach to single event transient analysis for highly complex design. J. Electron. Test. 29(3), 301–305 (2013)

    Article  Google Scholar 

  24. M.A. Aguirre, V. Baena, J. Tombs, M. Violante, A new approach to estimate the effect of single event transients in complex circuits. IEEE Trans. Nucl. Sci. 54(4), 1018–1024 (2007)

    Article  Google Scholar 

  25. M. García-Valderas, L. Entrena, R. Fernández-Cardenal, C. López-Ongil, M.P. García, SET emulation under a quantized delay model. J. Electron. Test. 25(1), 107–116 (2009)

    Article  Google Scholar 

  26. L. Entrena, M. García-Valderas, R. Fernández-Cardenal, M.P. García, C. López-Ongil, SET emulation considering electrical masking effects. IEEE Trans. Nucl. Sci. 56(4), 2015–2021 (2009)

    Article  Google Scholar 

  27. S. Pagliarini, F. Kastensmidt, L. Entrena, A. Lindoso, E. San Millán, Analyzing the impact of single-event-induced charge sharing in complex circuits. IEEE Trans. Nucl. Sci. 58(6), 2768–2775 (2011)

    Article  Google Scholar 

  28. L. Entrena, M. García-Valderas, R. Fernández-Cardenal, A. Lindoso, M. Portela García, C. López-Ongil, Soft error sensitivity evaluation of microprocessors by multilevel emulation-based fault injection. IEEE Trans. Comput. 61(3), 313–322 (2012)

    Article  MathSciNet  Google Scholar 

  29. L. Entrena, A. Lindoso, M. García-Valderas, M. Portela-García, C. López-Ongil, Analysis of SET effects in a PIC microprocessor for selective hardening. IEEE Trans. Nucl. Sci. 58(3), 1078–1085 (2011)

    Article  Google Scholar 

  30. L. Parra, A. Lindoso, M. Portela-Garcia, L. Entrena, B. Du, M.S. Reorda, L. Sterpone, A new hybrid nonintrusive error-detection technique using dual control-flow monitoring. IEEE Trans. Nucl. Sci. 61(6), 3236–3243 (2014)

    Article  Google Scholar 

  31. L. Entrena, A. Lindoso, E. San Millán, S. Pagliarini, F. Almeida, F. Kastensmidt, Constrained placement methodology for reducing SER under single-event-induced charge sharing effects. IEEE Trans. Nucl. Sci. 59(4), 811–817 (2012)

    Article  Google Scholar 

Download references

Acknowledgment

This work was supported in part by the Spanish Ministry of Economy and Competitiveness under project ESP2015-68245-C4-1-P.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Luis Entrena .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Entrena, L., García-Valderas, M., Lindoso, A., Portela-Garcia, M., San Millán, E. (2019). Fault Injection Methodologies. In: Velazco, R., McMorrow, D., Estela, J. (eds) Radiation Effects on Integrated Circuits and Systems for Space Applications. Springer, Cham. https://doi.org/10.1007/978-3-030-04660-6_6

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-04660-6_6

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-04659-0

  • Online ISBN: 978-3-030-04660-6

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics