Abstract
In this chapter, an efficient system-level approach to model and analyze the propagation of SEUs in a simple processor is introduced. The high-level model of the processor is formalized as a Continuous-Time Markov Chain (CTMC). Probabilistic model checking (PMC) is utilized to exhaustively estimate the impact of SEUs on the behavior of the processor. The proposed CTMC model is analyzed for different SEU injection scenarios and different bit-flip rates. Results demonstrate that the proposed approach can provide an accurate estimation of different metrics, such as Mean Time to Failure (MTTF), Mean Time to Recover(MTTR), Steady-State Availability (SSA), and the probability of failure for each SEU injection scenario in the system’s subcomponents. Furthermore, it is demonstrated that in comparison with existing simulation based analysis of fault impact evaluation, the presented approach is orders of magnitude faster in terms of analysis time.
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Ammar, M., Bany Hamad, G., Ait Mohamed, O., Savaria, Y. (2019). System-Level Modeling and Analysis of the Vulnerability of a Processor to Single-Event Upsets (SEUs). In: Velazco, R., McMorrow, D., Estela, J. (eds) Radiation Effects on Integrated Circuits and Systems for Space Applications. Springer, Cham. https://doi.org/10.1007/978-3-030-04660-6_2
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DOI: https://doi.org/10.1007/978-3-030-04660-6_2
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