Mitigation Transient Faults by Backward Error Recovery in SRAM-FPGA

  • Fakhreddine GhaffariEmail author
  • Olivier Romain
  • Bertrand Granado


This chapter focuses on the reliability of a specific class of systems on chip which are able to be reconfigured dynamically and partially. The possibility of using their Partial Dynamic Reconfiguration (PDR) capability for hardening applications on FPGAs is explored. We propose the use of checkpoint approaches and context restoration for tolerance against transient faults. PDR is used for managing the context of hardware tasks present on the application. The use of PDR reduces changes to the original system and therefore the complexity of the resulting system. After identifying the limitations of the “Backward Error Recovery” approach into SRAM-based FPGAs platforms, we propose a new resource placement algorithm on FPGA to minimize the access time needed by check-pointing and rolling back operations of hardware tasks. The evaluation of the overall reliability of this approach is achieved through fault injection campaigns on a demonstration platform running on a Virtex-5 that integrates the proposed reliability controller and hosts a data encryption application.


  1. 1.
    A. Putnam, et al., Catapult: a reconfigurable fabric for accelerating large-scale datacenter services, in 41st Annual International Symposium on Computer Architecture (ISCA), Minneapolis, USA, 13–18 June 2014Google Scholar
  2. 2.
    B. Zeidman, Designing with FPGAs and CPLDs (CRC Press, Boca Raton, FL, 2002)CrossRefGoogle Scholar
  3. 3.
    I. Kuon, J. Rose, Quantifying and Exploring the Gap between FPGAs and ASICs (Springer Science and Business Media, Boston, MA, 2010)CrossRefGoogle Scholar
  4. 4.
    Xilinx. Virtex-5 FPGA Configuration User Guide UG191 (v3.11), 2012Google Scholar
  5. 5.
    V. Betz, J. Rose, A. Marquardt, Architecture and Cad for Deep-Submicron FPGAs, vol 497 (Springer Science & Business Media, Boston, MA, 2012)Google Scholar
  6. 6.
    M. John, S. Smith, Application-Specific Integrated Circuits, 1st edn. (Addison Wesley, Boston, MA, 1997)Google Scholar
  7. 7.
    I. Kuon, R. Tessier, J. Rose. FPGA architecture: survey and challenges. Found Trends Electron Des Automat, vol. 2, nb. 2, pp. 135-253, 2008CrossRefGoogle Scholar
  8. 8.
    A. Amara, F. Amiel, T. Ea, FPGA vs. ASIC for low power applications. Microelectron J 37(8), 669–677 (2006)CrossRefGoogle Scholar
  9. 9.
    C.C. Yui, G.M. Swift, C. Carmichael, R. Koga, J.S. George, SEU mitigation testing of Xilinx VirtexII FPGAs, in IEEE Radiation Effects Data Workshop, Los Alamitos, USA, pp. 92–97, 21–25 July 2003Google Scholar
  10. 10.
    J. George, R. Koga, G. Swift, G. Allen, C. Carmichael, C.W. Tseng. Single event upsets in Xilinx Virtex-4 FPGA devices, in Radiation Effects Data Workshop, IEEE, Ponte Vedra Beach, USA, 2006, pp. 109–114Google Scholar
  11. 11.
    H. Quinn, K. Morgan, P. Graham, J. Krone, M. Caffrey, Static proton and heavy ion testing of the Xilinx Virtex-5 device, in Radiation Effects Data Workshop, vol 0, Honolulu, Hawaï, 23–27 July 2007, pp. 177–184Google Scholar
  12. 12.
    N. Battezzati, L. Sterpone, M. Violante, Monte Carlo analysis of the effects of soft errors accumulation in SRAM-based FPGAs. IEEE Transact Nucl Sci 55(6), 3381–3387 (2008)CrossRefGoogle Scholar
  13. 13.
    K. Iniewski, Radiation Effects in Semiconductors (CRC Press, Boca Raton, FL, 2010)CrossRefGoogle Scholar
  14. 14.
    J.A. Cheatham, J.M. Emmert, S. Baumgart, A survey of fault tolerant methodologies for FPGAs. ACM Trans. Des. Autom. Electron. Syst. 11(2), 501–533 (2006)CrossRefGoogle Scholar
  15. 15.
    P. Tröger, F. Salfner, S. Tschirpke, Software-implemented fault injection at firmware level, in International Conference on Dependability, Venice, Italy 18–25 July 2010, pp. 13–16Google Scholar
  16. 16.
    US Department of Defense, Electronic reliability design handbook. Report, MIL-HDBK-5H: Metallic Materials and Elements for Aerospace Vehicle Structures, 1998Google Scholar
  17. 17.
    F.L. Kastensmidt, L. Carro, R.A. da Luz Reis, Fault-Tolerance Techniques for SRAM-Based FPGAs (Springer Verlag, Berlin, 2006)Google Scholar
  18. 18.
    J. Mathew, R.A. Shafik, D.K. Pradhan, Energy-Efficient Fault-Tolerant Systems (Springer, New York, 2014)CrossRefGoogle Scholar
  19. 19.
    J. Johnson, W. Howes, M. Wirthlin, D.L. McMurtrey, M. Caffrey, P. Graham, K. Morgan, Using duplication with compare for on-line error detection in FPGA-based designs, in IEEE Aerospace Conference, Big Sky, Montana, USA, 1–8 March 2008, pp. 1–11Google Scholar
  20. 20.
    P. Hung-Manh, S. Pillement, S.J. Piestrak, Low-overhead fault-tolerance technique for a dynamically reconfigurable softcore processor. IEEE Transacts Comput 62(6), 1179–1192 (2013)MathSciNetCrossRefGoogle Scholar
  21. 21.
    N. Rollins, M. Fuller, M.J. Wirthlin, A comparison of fault-tolerant memories in SRAM-based FPGAs, in IEEE Aerospace Conference, Big Sky, Montana, USA, 6–13 March 2010, pp. 1–12Google Scholar
  22. 22.
    J.P. Anderson, B. Nelson, M. Wirthlin. Using statistical models with duplication and compare for reduced cost FPGA reliability, in IEEE Aerospace Conference, Big Sky, Montana, USA, 6–13 March 2010, pp. 1–8Google Scholar
  23. 23.
    S. Habinc, Functional triple modular redundancy (FTMR). Design and Assessment Report, 2002, pp. 1–56Google Scholar
  24. 24.
    M. Niknahad, O. Sander, J. Becker, Fine grain fault tolerance A key to high reliability for FPGAs in space, in Aerospace Conference, Big Sky, Montana, USA, Aerospace Conference, IEEE. Big Sky, Montana, USA, March 3–10, 2012, pp. 1–10Google Scholar
  25. 25.
    Y. Ichinomiya, S. Tanoue, M. Amagasaki, M. Iida, M. Kuga, T. Sueyoshi, Improving the robustness of a softcore processor against SEUs by using TMR and partial reconfiguration, in 18th IEEE International Symposium Field-Programmable Custom Computing Machines (FCCM), Charlotte, North Carolina, USA, 2–4 May 2010, pp. 47–54Google Scholar
  26. 26.
    A. H. Gholamipour, K. Papadimitriou, F. Kurdahi, A. Dollas, A. Eltawil. Area, reconfiguration delay and reliability trade-offs in designing reliable multi-mode FIR filters, in IEEE International Workshop on Design and Test (IDT), Beirut, Lebanon, 11–14 December 2011Google Scholar
  27. 27.
    S. Yousuf, A. Jacobs, A. Gordon-Ross, Partially reconfigurable system-on-chips for adaptive fault tolerance, in International Conference on Field-Programmable Technology (FPT), New Deli, India, 12–14 December 2011, pp. 1–8Google Scholar
  28. 28.
    L. Sterpone, A. Ullah, On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs, in NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2013, pp. 9–14Google Scholar
  29. 29.
    P.K. Samudrala, J. Ramos, S. Katkoori, Selective triple modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs. IEEE Trans. Nucl. Sci. 51(5), 2957–2969 (2004)CrossRefGoogle Scholar
  30. 30.
    B. Pratt, M. Caffrey, J.F. Carroll, P. Graham, K. Morgan, M. Wirthlin, Fine-grain SEU mitigation for FPGAs using partial TMR. IEEE Trans. Nucl. Sci. 55(4), 2274–2280 (2008)CrossRefGoogle Scholar
  31. 31.
    R.H. Morelos-Zaragoza, The Art of Error Correcting Coding (John Wiley and Sons, Hoboken, NJ, 2006)CrossRefGoogle Scholar
  32. 32.
    H. Keheng, Y. Hu, X. Li, H. Gengxin, L. Hongjin, L. Bo, Exploiting free LUT entries to mitigate soft errors in SRAM-based FPGAs, in Asian Test Symposium (ATS), New Delhi, India, 20–23 November 2011, pp. 438–443Google Scholar
  33. 33.
    R.W. Hamming, Error detecting and error correcting codes. Bell Syst Tech J 29(2), 147–160 (1950)MathSciNetCrossRefGoogle Scholar
  34. 34.
    K.S. Morgan, D.L. McMurtrey, B.H. Pratt, M.J. Wirthlin, A comparison of TMR with alternative fault-tolerant design techniques for FPGAs. IEEE Transact Nucl Sci 54(6), 2065–2072 (2007)CrossRefGoogle Scholar
  35. 35.
    Xilinx Application Notes XAPP216, Correcting single-event upset through Virtex partial reconfiguration, 2000Google Scholar
  36. 36.
    J. Heiner, B. Sellers, M. Wirthlin, J. Kalb, FPGA partial reconfiguration via configuration scrubbing, in IEEE International Conference on Field Programmable Logic and Applications (FPL), Prague, Czech Republic, 31 August–2 September 2009, pp. 99–104,Google Scholar
  37. 37.
    S. Liu, R.N. Pittman, A. Forin, J.-L. Gaudiot, Achieving energy efficiency through runtime partial reconfiguration on reconfigurable systems. ACM Transact Embed Comput Syst 12(3), 1–21 (2013)Google Scholar
  38. 38.
    B. Dutton, C. Stroud. Single event upset detection and correction in Virtex-4 and Virtex-5 FPGAs, in ISCA International Conference on Computers and their Applications (ISCA), New Orleans, Louisiana, 8–10 April 2009, pp. 57–62Google Scholar
  39. 39.
    Xilinx. Partial Reconfiguration User Guide UG702 (v12.1), 2010Google Scholar
  40. 40.
    F. Ghaffari, F. Sahraoui, M. El Amine Benkhelifa, B. Granado, M. A. Kacou, O. Romain. Fast SRAM-FPGA fault injection platform based on dynamic partial reconfiguration, in 26th International Conference on Microelectronics (ICM), 2014, pp. 144–147Google Scholar
  41. 41.
    F. Sahraoui, F. Ghaffari, M. El Amine Benkhelifa, B. Granado, Reliability assessment of backward error recovery for SRAM-based FPGAs, in International Symposium on Design and Test (IDT), Algier, Algeria, 16–18 December 2014, pp. 248–252Google Scholar
  42. 42.
    F. Sahraoui, F. Ghaffari, M. El Amine Benkhelifa, B. Granado. An efficient BER-based reliability method for SRAM-based FPGA, in International Symposium Design and Test (IDT), Marrakesh, Morocco, 16–18 December 2013, pp. 1–6Google Scholar
  43. 43.
    M. Berg, C. Poivey, D. Petrick, D. Espinosa, A. Lesea, K.A. LaBel, M. Friendlich, H. Kim, A. Phan, Effectiveness of internal versus external SEU scrubbing mitigation strategies in a Xilinx FPGA: design, test, and analysis. IEEE Transact Nucl Sci 55(4), 2259–2266 (2008)CrossRefGoogle Scholar
  44. 44.
    Xilinx. LogiCORE IP XPS HWICAP (v5.00a), 2010Google Scholar
  45. 45.
    C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson, B. Hutchings, Rapidsmith: do-it-yourself cad tools for xilinx fpgas, in Proceedings of the 2011 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2011, pp. 349–355Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Fakhreddine Ghaffari
    • 1
    Email author
  • Olivier Romain
    • 1
  • Bertrand Granado
    • 2
  1. 1.ETIS, UMR-8051Université Paris Seine, Université de Cergy-Pontoise, ENSEA, CNRSCergy-PontoiseFrance
  2. 2.LIP6Sorbonne Université, CNRS UMR 7606ParisFrance

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