Packages

Abstract

One of the drawbacks of the VHDL standard package is that it provides limited functionality in its synthesizable data types. The bit and bit_vector, while synthesizable, lack the ability to accurately model many of the topologies implemented in modern digital systems. Of primary interest are topologies that involve multiple drivers connected to a single wire. The standard package will not permit this type of connection; however, this type of topology is a common way to interface multiple nodes on a shared interconnection. Furthermore, the standard package does not provide many useful features for these types, such as don’t cares, arithmetic using the + and − operators, type conversion functions, or the ability to read/write external files. To increase the functionality of VHDL, packages are included in the design. This chapter introduces the most common packages used in modern VHDL models.