Abstract
This chapter presents a set of built-in operators that will allow logic to be modeled within the VHDL architecture. This chapter then presents a series of combinational logic model examples.
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© 2019 Springer Nature Switzerland AG
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LaMeres, B.J. (2019). Modeling Concurrent Functionality. In: Quick Start Guide to VHDL. Springer, Cham. https://doi.org/10.1007/978-3-030-04516-6_3
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DOI: https://doi.org/10.1007/978-3-030-04516-6_3
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Publisher Name: Springer, Cham
Print ISBN: 978-3-030-04515-9
Online ISBN: 978-3-030-04516-6
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