Abstract
Counters are a special case of finite state machines because they move linearly through their discrete states (either forward or backward) and typically are implemented with state-encoded outputs. Due to this simplified structure and widespread use in digital systems, VHDL allows counters to be modeled using a single process and with arithmetic operators (i.e., + and −). This enables a more compact model and allows much wider counters to be implemented. This chapter will cover some of the most common techniques for modeling counters.
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LaMeres, B.J. (2019). Modeling Counters. In: Quick Start Guide to VHDL. Springer, Cham. https://doi.org/10.1007/978-3-030-04516-6_10
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DOI: https://doi.org/10.1007/978-3-030-04516-6_10
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Publisher Name: Springer, Cham
Print ISBN: 978-3-030-04515-9
Online ISBN: 978-3-030-04516-6
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