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Deterministic Approaches to Bitstream Computing

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Stochastic Computing: Techniques and Applications
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Abstract

Stochastic logic allows complex arithmetic to be performed with very simple logic, but it suffers from high latency and poor precision. Furthermore, the results are always somewhat inaccurate due to random fluctuations. The random or pseudorandom sources required to generate the representation are costly, consuming a majority of the circuit area (and diminishing the overall gains in area). This chapter reexamines the foundations of stochastic computing and comes to some surprising conclusions. It demonstrates that one can compute deterministically using the same structures that are used to compute stochastically. In doing so, the latency is reduced by an exponential factor; also, the area is reduced significantly (and this correlates with a reduction in power); and finally, one obtains completely accurate results, with no errors or uncertainty. This chapter also explores an alternate view of this deterministic approach. Instead of viewing signals as digital bit streams, we can view them as periodic signals, with the value encoded as the fraction of the time that the signal is in the high (on) state compared to the low (off) state in each cycle. Thus we have a time-based encoding. All of the constructs developed for stochastic computing can be used to compute on these periodic signals, so the designs are very efficient in terms of area and power. Given how precisely values can be encoded in the time, the method could produce designs that have much lower latency that conventional ones.

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References

  1. M. H. Najafi, P. Li, D. J. Lilja, W. Qian, K. Bazargan, and M. Riedel, “A reconfigurable architecture with sequential logic-based stochastic computing,” J. Emerg. Technol. Comput. Syst., vol. 13, no. 4, pp. 57:1–57:28, June 2017. [Online]. Available: http://doi.acm.org/10.1145/3060537

  2. E. Friedman, “Clock distribution networks in synchronous digital integrated circuits,” Proceedings of the IEEE, vol. 89, no. 5, pp. 665–692, May 2001.

    Article  Google Scholar 

  3. Y. Jiang, H. Zhang, H. Zhang, H. Liu, X. Song, M. Gu, and J. Sun, “Design of mixed synchronous/asynchronous systems with multiple clocks,” Parallel and Distributed Systems, IEEE Transactions on, vol. PP, no. 99, pp. 1–1, 2014.

    Google Scholar 

  4. A. Alaghi and J. P. Hayes, “Survey of stochastic computing,” ACM Transaction on Embedded Computing, vol. 12, 2013.

    Article  Google Scholar 

  5. W. Qian, “Digital yet deliberately random: Synthesizing logical computation on stochastic bit streams,” Ph.D. dissertation, University of Minnesota, 2011.

    Google Scholar 

  6. N. C. Laurenciu and S. D. Cotofana, “Low cost and energy, thermal noise driven, probability modulated random number generator,” in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 2015, pp. 2724–2727.

    Google Scholar 

  7. S. Balatti, S. Ambrogio, R. Carboni, V. Milo, Z. Wang, A. Calderoni, N. Ramaswamy, and D. Ielmini, “Physical unbiased generation of random numbers with coupled resistive switching devices,” IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 2029–2035, May 2016.

    Article  Google Scholar 

  8. N. Rangarajan, A. Parthasarthy, N. Kani, and S. Rakheja, “Voltage-tunable stochastic computing with magnetic bits,” in 2017 IEEE International Magnetics Conference (INTERMAG), April 2017, pp. 1–2.

    Google Scholar 

  9. R. D’Angelo and S. Sonkusale, “Analogue multiplier using passive circuits and digital primitives with time-mode signal representation,” Electronics letters, vol. 51, pp. 1754–1755, 2015.

    Article  Google Scholar 

  10. V. Ravinuthula, V. Garg, J. G. Harris, and J. Fortes, “Time-mode circuits for analog computation,” International Journal of Circuit Theory and Applications, vol. 37, pp. 631–659, 2009.

    Article  Google Scholar 

  11. K. M. Mhaidat, M. A. Jabri, and D. W. Hammerstrom, “Representation, methods, and circuits for time-based conversion and computation,” International Journal of Circuit Theory and Applications, vol. 39, pp. 299–311, 2011.

    Article  Google Scholar 

  12. Y. P. Tsividis and J. O. Voorman, Eds., Integrated Continous-Time Filters: Principles, Design and Applications. iEEE Press, 1993.

    Google Scholar 

  13. M. H. Najafi and D. J. Lilja, “High-speed stochastic circuits using synchronous analog pulses,” in ASP-DAC 2017, 22nd Asia and South Pacific Design Automation Conference, 2017.

    Google Scholar 

  14. M. H. Najafi, S. Jamali-Zavareh, D. J. Lilja, M. D. Riedel, K. Bazargan, and R. Harjani, “Time-encoded values for highly efficient stochastic circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 5, pp. 1644–1657, May 2017.

    Article  Google Scholar 

  15. K. Cushon, C. Leroux, S. Hemati, S. Mannor, and W. J. Gross, “A min-sum iterative decoder based on pulsewidth message encoding,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 11, pp. 893–897, Nov 2010.

    Article  Google Scholar 

  16. I. T. R. for Semiconductors (ITRS), “Itrs 2.0,” 2015.

    Google Scholar 

  17. G. W. Roberts and M. Ali-Bakhshian, “A brief introduction to time-to-digital and digital-to-time converters,” IEEE Transactions on Circuits and System-II, vol. 57, no. 3, pp. 153–157, January 2010.

    Article  Google Scholar 

  18. P. Li, D. Lilja, W. Qian, K. Bazaragan, and M. D. Riedel, “The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic,” in International Conference on Computer-Aided Design, 2012, pp. 480–487.

    Google Scholar 

  19. W. Qian, X. Li, M. D. Riedel, K. Bazargan, and D. J. Lilja, “An architecture for fault-tolerant computation with stochastic logic,” IEEE Transactions on Computers, vol. 60, no. 1, pp. 93–105, 2011.

    Article  MathSciNet  Google Scholar 

  20. W. Qian and M. D. Riedel, “The synthesis of robust polynomial arithmetic with stochastic logic,” in Design Automation Conference, 2008, pp. 648–653.

    Google Scholar 

  21. W. Qian, M. D. Riedel, K. Barzagan, and D. Lilja, “The synthesis of combinational logic to generate probabilities,” in International Conference on Computer-Aided Design, 2009, pp. 367–374.

    Google Scholar 

  22. W. Qian, M. D. Riedel, H. Zhou, and J. Bruck, “Transforming probabilities with combinational logic,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (to appear), 2011.

    Google Scholar 

  23. W. Qian, C. Wang, P. Li, D. Lilja, K. Bazaragan, and M. D. Riedel, “An efficient implementation of numerical integration using logical computation on stochastic bit streams,” in International Conference on Computer-Aided Design, 2012, pp. 156–162.

    Google Scholar 

  24. A. Alaghi and J. P. Hayes, “On the functions realized by stochastic computing circuits,” in Proceedings of the 25th Edition on Great Lakes Symposium on VLSI, ser. GLSVLSI ’15. New York, NY, USA: ACM, 2015, pp. 331–336. [Online]. Available: http://doi.acm.org/10.1145/2742060.2743758

  25. S. S. Tehrani, A. Naderi, G.-A. Kamendje, S. Hemati, S. Mannor, and W. J. Gross, “Majority-based tracking forecast memories for stochastic ldpc decoding,” IEEE Transactions on Signal Processing, vol. 58, pp. 4883–4896, 2010.

    Article  MathSciNet  Google Scholar 

  26. B. Gaines, “Stochastic computing systems,” in Advances in Information Systems Science. Plenum Press, 1969, vol. 2, ch. 2, pp. 37–172.

    Google Scholar 

  27. B. Brown and H. Card, “Stochastic neural computation I: Computational elements,” IEEE Transactions on Computers, vol. 50, no. 9, pp. 891–905, 2001.

    Article  MathSciNet  Google Scholar 

  28. P. Li, D. J. Lilja, W. Qian, K. Bazargan, and M. D. Riedel, “Case studies of logical computation on stochastic bit streams,” in Lecture Notes in Computer Science: Proceedings of Power and Timing Modeling, Optimization and Simulation Workshop, G. Goos, J. Hartmanis, and J. Leeuwen, Eds. Springer, 2012.

    Google Scholar 

  29. P. Li, W. Qian, and D. J. Lilja, “A stochastic reconfigurable architecture for fault-tolerant computation with sequential logic,” IEEE 30th International Conference on Computer Design (ICCD), 2012.

    Google Scholar 

  30. M. H. Najafi and D. Lilja, “High quality down-sampling for deterministic approaches to stochastic computing,” IEEE Transactions on Emerging Topics in Computing, pp. 1–1, 2018.

    Google Scholar 

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Correspondence to Marc Riedel .

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Riedel, M. (2019). Deterministic Approaches to Bitstream Computing. In: Gross, W., Gaudet, V. (eds) Stochastic Computing: Techniques and Applications. Springer, Cham. https://doi.org/10.1007/978-3-030-03730-7_6

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  • DOI: https://doi.org/10.1007/978-3-030-03730-7_6

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