Abstract
Low Power VLSI design has become the most important challenge of present chip designs. Advances in chip fabrication have made possible to design chips at high integration and fast performance. Reducing power consumption and increasing noise margin have become two major concerns in every stage of SRAM designs. In this paper the 6T and 8T SRAM cells are constructed using High-K Metal Gate and FinFET for low power embedded memory applications. These SRAM cells’ performance are analyzed and compared in terms of basic parameters, such as power consumption and static noise margin (SNM).
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Gopal, M., Prasad, D.S., Raj, B.: 8T SRAM cell design for dynamic and leakage power reduction. Int. J. Comput. Appl. 71(9), 0975–8887 (2013)
Rahman, N., Singh, B.P.: Design and verification of low power SRAM using 8T SRAM cell approach. Int. J. Comput. Appl. 67(18), 0975–8887 (2013). Department of electronics and communication FET-MITS (Deemed university), Lakshmangarh, India
Pal, P.K., Kaushik, B.K., Dasgupta, S.: Design metrics improvement for SRAMs using symmetric dual-k spacer (SymD-k) FinFETs. IEEE Trans. Electron Devices 61(4), 1123 (2014)
Kushwah, C.B., Vishvakarma, S.K.: A sub-threshold eight transistor (8T) SRAM cell design for stability improvement. Nanoscale Devices and VLSI/ULSI Circuit and System Design Lab, Electrical Engineering, Indian Institute of Technology, Indore, M.P., India
Rahman, N., Singh, B.P.: Design of low power SRAM memory using 8T SRAM cell. Int. J. Recent Technol. Eng. 2(1), 123 (2013). ISSN: 2277–3878
Pasandi, G., Fakhraie, S.M.: An 8T low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FinFETs. IEEE Trans. Electron Devices 61(7), 235 (2014)
Kang, S.M., Leblebici, Y.: CMOS Digital Integrated Circuits Analysis and Design. Tata McGraw-Hill Education, New Delhi (2003)
Yeo, K.S., Roy, K.: Low – Voltage, Low – Power VLSI Subsystems. McGraw-Hill, New York (2005)
Baker, R.J.: CMOS: Circuit Design, Layout, and Simulation, vol. 1, 3rd edn. Wiley, New York (2010)
HSPICE LAB Manual – VSD Centre, by M. S. Ramaiah School of Advanced Studies
HSPICE® Simulation and Analysis User Guide, by Synopsis
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this paper
Cite this paper
Nachappa, S.M., Jeevitha, A.S., Vasundara Patel, K.S. (2019). Comparative Analysis of Digital Circuits Using 16 nm FinFET and HKMG PTM Models. In: Arai, K., Kapoor, S., Bhatia, R. (eds) Advances in Information and Communication Networks. FICC 2018. Advances in Intelligent Systems and Computing, vol 886. Springer, Cham. https://doi.org/10.1007/978-3-030-03402-3_7
Download citation
DOI: https://doi.org/10.1007/978-3-030-03402-3_7
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-03401-6
Online ISBN: 978-3-030-03402-3
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)