Abstract
Digital circuits are large and commonly range in millions of gates. It is common to find ASIC chips or SoC chips with several million or more gates. Testing digital circuits for manufacturing defects can be a daunting task. Finding a manufacturing defect within the millions of gates and its millions of interconnects is a difficult and near impossible task without the help of proper testing methodology.
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Lee, W.F. (2019). Design for Test. In: Learning from VLSI Design Experience . Springer, Cham. https://doi.org/10.1007/978-3-030-03238-8_5
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DOI: https://doi.org/10.1007/978-3-030-03238-8_5
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Publisher Name: Springer, Cham
Print ISBN: 978-3-030-03237-1
Online ISBN: 978-3-030-03238-8
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