Abstract
Latch inference refers to the condition whereby latches are inserted by synthesis tool to enable a signal to maintain its previous value. Inferring latches in a design is not desirable as it unnecessarily increases the size of the design. A bigger design will translate to a higher cost. A bigger design will also increase probability of defect and thereby reducing yield.
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Lee, W.F. (2019). Latch Inference. In: Learning from VLSI Design Experience . Springer, Cham. https://doi.org/10.1007/978-3-030-03238-8_4
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DOI: https://doi.org/10.1007/978-3-030-03238-8_4
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