Abstract
The principal theme in present world of electronic is low power design. In modern technologies, low power design has drawn significant concern due to increasing transistor counts, higher speed of operations and clock frequencies. Reversible logic plays a vital role when VLSI circuits with minimal power dissipation are considered. It has the ability to decrease the power dissipation by recuperating bit loss from its distinctive one to one mapping. This paper presents a novel design of Recursive Systematic Convolutional (RSC) Encoder using the existing reversible gates. The proposed RSC encoder is coded in Verilog-HDL and synthesized in synopsis DC tool (90 nm library). The power analysis report shows that the proposed RSC encoder circuit dissipates less power when compared to the conventional one.
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Aishvarya, J., Manindra, P.S.N.V.V.S., Sathya Priya, P., Rao, K.V., Prabhu, E. (2019). Design of Low Power RSC Encoder Using Reversible Logic. In: Hemanth, J., Fernando, X., Lafata, P., Baig, Z. (eds) International Conference on Intelligent Data Communication Technologies and Internet of Things (ICICI) 2018. ICICI 2018. Lecture Notes on Data Engineering and Communications Technologies, vol 26. Springer, Cham. https://doi.org/10.1007/978-3-030-03146-6_22
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DOI: https://doi.org/10.1007/978-3-030-03146-6_22
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