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Abstract

High-level power models have been investigated by researchers in academia and by industry. The works can be divided into two groups: those with a strong connection to register transfer level code and true electronic system level approaches. The latter group can be subdivided into three topics. First, the internal structure of the power models is different. Some power models are based on a state machine with a fixed power consumption value attributed to each state. Other power models are basically a linear equation in which coefficients are multiplied with input parameters. The coefficients are fixed power or energy values and the inputs are, for example, event counts from a timed functional simulation. Some power models go beyond this approach and use higher order terms or multiple linear formulas. The second topic is about the connection of power models to existing simulations. There are several frameworks that support this, both from academia and from industry. Third, the actual creation of power models as well as their application and evaluation for certain specific components is covered in many papers. The majority handles programmable application processors by using different modeling strategies. Some others focus on power estimation for networks on chip. However, also the power consumption of peripherals, buses, memories, and even software libraries has been modeled on high level.

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References

  1. Atitallah RB, Niar S, Dekeyser JL (2007) MPSoC power estimation framework at transaction level modeling. In: International conference on microelectronics, pp 245–248. https://doi.org/10.1109/ICM.2007.4497703

  2. Bazzaz M, Salehi M, Ejlali A (2013) An accurate instruction-level energy estimation model and tool for embedded systems. IEEE Trans Instrum Meas 62(7):1927–1934. https://doi.org/10.1109/TIM.2013.2248288

    Article  Google Scholar 

  3. Beltrame G, Sciuto D, Silvano C (2007) Multi-accuracy power and performance transaction-level modeling. IEEE Trans. Comput Aided Des Integr Circuits Syst 26(10):1830–1842. https://doi.org/10.1109/TCAD.2007.895790

    Article  Google Scholar 

  4. Benini L, Bogliolo A, Favalli M, Micheli GD (1998) Regression models for behavioral power estimation. IOS J Integr Comput-Aided Eng 5(2):95–106

    Article  Google Scholar 

  5. Benini L, Hodgson R, Siegel P (1998) System-level power estimation and optimization. In: International symposium on low power electronics and design, ISLPED’98, pp 173–178. ACM, New York. https://doi.org/10.1145/280756.280881

    Google Scholar 

  6. Bombieri N, Fummi F, Guarnieri V, Acquaviva A (2012) Energy aware TLM platform simulation via RTL abstraction. In: 2012 IEEE international high level design validation and test workshop (HLDVT), pp 156–163. https://doi.org/10.1109/HLDVT.2012.6418258

  7. Bouhadiba T, Moy M, Maraninchi F (2013) System-level modeling of energy in TLM for early validation of power and thermal management. In: Design, automation test in Europe conference exhibition (DATE), pp 1609–1614. https://doi.org/10.7873/DATE.2013.327

  8. Bouhadiba T, Moy M, Maraninchi F, Cornet J, Maillet-Contoz L, Materic I (2013) Co-simulation of functional SystemC TLM models with power/thermal solvers. In: 2013 IEEE international symposium on parallel distributed processing, workshops and PhD forum, pp 2176–2181. https://doi.org/10.1109/IPDPSW.2013.206

  9. Brooks D, Tiwari V, Martonosi M (2000) Wattch: a framework for architectural-level power analysis and optimizations. In: Proceedings of the 27th annual international symposium on computer architecture, ISCA’00. ACM, New York, pp 83–94. https://doi.org/10.1145/339647.339657

    Google Scholar 

  10. Burger D, Austin TM (1997) The SimpleScalar tool set, version 2.0. SIGARCH Comput Archit News 25(3):13–25. https://doi.org/10.1145/268806.268810

    Article  Google Scholar 

  11. Castillo J, Posadas H, Villar E, Martínez M (2007) Energy consumption estimation technique in embedded processors with stable power consumption based on source-code operator energy figures. In: XXII conference on design of circuits and integrated systems

    Google Scholar 

  12. Chan J, Parameswaran S (2005) NoCEE: energy macro-model extraction methodology for network on chip routers. In: IEEE/ACM international conference on computer-aided design (ICCAD), pp 254–259. https://doi.org/10.1109/ICCAD.2005.1560073

  13. Diop T, Jerger NE, Anderson J (2014) Power modeling for heterogeneous processors. In: Proceedings of workshop on general purpose processing using GPUs, GPGPU-7. ACM, New York, pp 90:90–90:98. https://doi.org/10.1145/2576779.2576790; http://doi.acm.org/10.1145/2576779.2576790

  14. Eeckhout L, Bosschere KD (2001) Early design phase power/performance modeling through statistical simulation. In: International symposium on performance analysis of systems and software. IEEE, Piscataway, pp 10–17. https://doi.org/10.1109/ISPASS.2001.990669

    Google Scholar 

  15. Eisley N, Soteriou V, Peh LS (2006) High-level power analysis for multi-core chips. In: Proceedings of the 2006 international conference on compilers, architecture and synthesis for embedded systems, CASES’06. ACM, New York, pp 389–400. https://doi.org/10.1145/1176760.1176807

    Chapter  Google Scholar 

  16. Eker J, Janneck JW, Lee EA, Liu J, Liu X, Ludvig J, Neuendorffer S, Sachs S, Xiong Y (2003) Taming heterogeneity - the Ptolemy approach. Proc IEEE 91(1):127–144. https://doi.org/10.1109/JPROC.2002.805829

    Article  Google Scholar 

  17. Fornaciari W, Gubian P, Sciuto D, Silvano C (1998) Power estimation of embedded systems: a hardware/software codesign approach. IEEE Trans Very Large Scale Integr (VLSI) Syst 6(2):266–275. https://doi.org/10.1109/92.678887

    Article  Google Scholar 

  18. Garcia ABA, Gobert J, Dombek T, Mehrez H, Petrot F (2002) Cycle-accurate energy estimation in system level descriptions of embedded systems. In: 9th international conference on electronics, circuits and systems, vol 2, pp 549–552. https://doi.org/10.1109/ICECS.2002.1046224

  19. Givargis TD, Vahid F, Henkel J (2000) Fast cache and bus power estimation for parameterized system-on-a-chip design. In: Proceedings design, automation and test in Europe, pp 333–338. https://doi.org/10.1109/DATE.2000.840292

  20. Givargis TD, Vahid F, Henkel J (2002) Instruction-based system-level power evaluation of system-on-a-chip peripheral cores. Very Large Scale Integr Syst 856–863. https://doi.org/10.1109/TVLSI.2002.808443

    Article  Google Scholar 

  21. Greaves D, Yasin M (2014) TLM POWER3: power estimation methodology for SystemC TLM 2.0. Springer, Berlin, pp 53–68. https://doi.org/10.1007/978-3-319-01418-0_4

    Google Scholar 

  22. Grüttner K, Hylla K, Rosinger S, Nebel W (2010) Towards an ESL framework for timing and power aware rapid prototyping of HW/SW systems. In: Forum on specification design languages (FDL), pp 1–6. https://doi.org/10.1049/ic.2010.0129

  23. Grüttner K, Hartmann PA, Hylla K, Rosinger S, Nebel W, Herrera F, Villar E, Brandolese C, Fornaciari W, Palermo G, Ykman-Covreur C, Quaglia D, Ferrero F, Velencia R (2012) COMPLEX: Codesign and power management in platform-based design space exploration. In: 15th Euromicro conference on digital system design, pp 349–358. https://doi.org/10.1109/DSD.2012.31

  24. Grüttner K, Hartmann PA, Fandrey T, Hylla K, Lorenz D, Stattelmann S, Sander B, Bringmann O, Nebel W, Rosenstiel W (2014) An ESL timing and power estimation and simulation framework for heterogeneous SoCs. In: International conference on embedded computer systems: architectures, modeling, and simulation, pp 181–190. https://doi.org/10.1109/SAMOS.2014.6893210

  25. Hamming RW (1950) Error detecting and error correcting codes. Bell Syst Tech. J 29:147–160. https://doi.org/10.1002/j.1538-7305.1950.tb00463.x

    Article  MathSciNet  Google Scholar 

  26. Helmstetter C, Moy M (2013) LIBTLMPWT: Model power-consumption and temperature in SystemC/TLM. http://www-verimag.imag.fr/~moy/?LIBTLMPWT-Model-Power-Consumption, Retrieved 1 April 2017

  27. Hill MD, Larus JR, Lebeck AR, Talluri M, Wood DA (1993) Wisconsin architectural research tool set. SIGARCH Comput Archit News 21(4):8–10. https://doi.org/10.1145/165496.165500

    Article  Google Scholar 

  28. Hsu CW, Liao JL, Fang SC, Weng CC, Huang SY, Hsieh WT, Yeh JC (2011) Power depot: integrating IP-based power modeling with ESL power analysis for multicore SoC designs. In: Proceedings of the 48th design and automation conference, vol 10121. ACM, New York, pp 47–52

    Google Scholar 

  29. Hu J, Marculescu R (2003) Energy-aware mapping for tile-based NoC architectures under performance constraints. In: Proceedings of the ASP-DAC Asia and South Pacific design automation conference, pp 233–239. https://doi.org/10.1109/ASPDAC.2003.1195022

  30. Hylla K, Hartmann PA, Helms D, Nebel W (2013) Early power and timing estimation of custom hardware blocks based on automatically generated combinatorial macros. In: 16th workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)

    Google Scholar 

  31. Ibrahim MEA, Rupp M, Fahmy HAH (2008) Power estimation methodology for VLIW digital signal processors. In: 2008 42nd Asilomar conference on signals, systems and computers, pp 1840–1844. https://doi.org/10.1109/ACSSC.2008.5074746

  32. IEEE (2016) IEEE standard for design and verification of low-power, energy-aware electronic systems. IEEE Std 1801–2015 (Revision of IEEE Std 1801–2013) pp 1–515. https://doi.org/10.1109/IEEESTD.2016.7445797

  33. Intel Docea (2017) Intel Docea power and thermal modeling and simulation solutions. http://www.intel.com/content/www/us/en/system-modeling-and-simulation/docea/overview.html, Retrieved 26 March 2017

  34. Julien N, Laurent J, Senn E, Martin E (2003) Power consumption modeling and characterization of the TI C6201. Micro IEEE 23(5):40–49. https://doi.org/10.1109/MM.2003.1240211

    Article  Google Scholar 

  35. Jung M, Weis C, Bertram P, Braun G, Wehn N (2013) Power modelling of 3D-stacked memories with TLM2.0 based virtual platforms. In: Synopsys user group conference, Munich, Germany

    Google Scholar 

  36. Jung M, Weis C, Wehn N, Chandrasekar K (2013) TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration. In: Workshop on rapid simulation and performance evaluation: methods and tools. ACM, New York. https://doi.org/10.1145/2432516.2432521

  37. Kahn G (1974) The semantics of a simple language for parallel programming. In: Information processing. North Holland, Amsterdam, pp 471–475

    Google Scholar 

  38. Kahng AB, Li B, Peh LS, Samadi K (2009) ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration. In: 2009 design, automation test in Europe conference exhibition, pp 423–428. https://doi.org/10.1109/DATE.2009.5090700

  39. Kahng AB, Li B, Peh LS, Samadi K (2012) ORION 2.0: a power-area simulator for interconnection networks. IEEE Trans Very Large Scale Integr (VLSI) Syst 20(1):191–196. https://doi.org/10.1109/TVLSI.2010.2091686

    Article  Google Scholar 

  40. Kalla P, Henkel J, Hu XS (2003) SEA: fast power estimation for micro-architectures. In: Proceedings of the ASP-DAC Asia and South Pacific design automation conference, pp 600–605. https://doi.org/10.1109/ASPDAC.2003.1195095

  41. Kavvadias N, Neofotistos P, Nikolaidis S, Kosmatopoulos CA, Laopoulos T (2004) Measurements analysis of the software-related power consumption in microprocessors. IEEE Trans Instrum Meas 53(4):1106–1112. https://doi.org/10.1109/TIM.2004.830784

    Article  Google Scholar 

  42. Konstantakos V, Chatzigeorgiou A, Nikolaidis S, Laopoulos T (2008) Energy consumption estimation in embedded systems. IEEE Trans Instrum Meas 57(4):797–804. https://doi.org/10.1109/TIM.2007.913724

    Article  Google Scholar 

  43. Koohi S, Mirza-Aghatabar M, Hessabi S, Pedram M (2008) High-level modeling approach for analyzing the effects of traffic models on power and throughput in mesh-based NoCs. In: 21st international conference on VLSI design (VLSID 2008), pp 415–420. https://doi.org/10.1109/VLSI.2008.40

  44. Laurent J, Senn E, Julien N, Martin E (2001) High level energy estimation for DSP systems. In: Proceedings of international workshop on power and timing modeling and optimization and simulation PATMOS01, pp 3.1.1–3.1.10

    Google Scholar 

  45. Laurent J, Julien N, Senn E, Martin E (2004) Functional level power analysis: an efficient approach for modeling the power consumption of complex processors. In: Proceedings of the conference on design, automation and test in Europe - Volume 1, DATE’04. IEEE Computer Society, Washington, p 10666. https://doi.org/10.1109/DATE.2004.1268921

  46. Lee MTC, Tiwari V, Malik S, Fujita M (1995) Power analysis and low-power scheduling techniques for embedded DSP software. In: Proceedings of the eighth international symposium on system synthesis, pp 110–115. https://doi.org/10.1109/ISSS.1995.520621

  47. Lee MTC, Tiwari V, Malik S, Fujita M (1997) Power analysis and minimization techniques for embedded DSP software. IEEE Trans Very Large Scale Integr (VLSI) Syst 5(1):123–135. https://doi.org/10.1109/92.555992

    Article  Google Scholar 

  48. Lee S, Ermedahl A, Min SL, Chang N (2001) An accurate instruction-level energy consumption model for embedded RISC processors. In: Proceedings of the ACM SIGPLAN workshop on languages, compilers and tools for embedded systems, LCTES’01. ACM, New York, pp 1–10. https://doi.org/10.1145/384197.384201

    Google Scholar 

  49. Lee D, Ishihara T, Muroyama M, Yasuura H, Fallah F (2006) An energy characterization framework for software-based embedded systems. In: IEEE/ACM/IFIP workshop on embedded systems for real time multimedia, pp 59–64. https://doi.org/10.1109/ESTMED.2006.321275

  50. Lee I, Kim H, Yang P, Yoo S, Chung EY, Choi KM, Kong JT, Eo SK (2006) PowerViP: SoC power estimation framework at transaction level. In: Asia and South Pacific conference on design automation. https://doi.org/10.1109/ASPDAC.2006.1594743

  51. Lee SE, Bagherzadeh N (2009) A high level power model for network-on-chip (NoC) router. Comput Electr Eng 35(6):837–845. https://doi.org/10.1016/j.compeleceng.2008.11.023. High performance computing architectures HPCA

    Article  MATH  Google Scholar 

  52. Li Y, Henkel J (1998) A framework for estimating and minimizing energy dissipation of embedded HW/SW systems. In: Proceedings of the 35th design and automation conference, pp 188–193. https://doi.org/10.1109/DAC.1998.724464

  53. Loghi M, Benini L, Poncino M (2004) Analyzing power consumption of message passing primitives in a single-chip multiprocessor. In: IEEE international conference on computer design: VLSI in computers and processors (ICCD), pp 393–396. https://doi.org/10.1109/ICCD.2004.1347952

  54. Loghi M, Benini L, Poncino M (2007) Power macromodeling of MPSoC message passing primitives. ACM Trans Embed Comput Syst 6(4). https://doi.org/10.1145/1274858.1274869

    Article  Google Scholar 

  55. Lorenz D, Grüttner K, Bombieri N, Guarnieri V, Bocchio S (2012) From RTL IP to functional system-level models with extra-functional properties. In: Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS’12. ACM, New York, pp 547–556. https://doi.org/10.1145/2380445.2380529

    Chapter  Google Scholar 

  56. Marcon CAM, Moreno EI, Calazans NLV, Moraes FG (2008) Comparison of network-on-chip mapping algorithms targeting low energy consumption. IET IEE Comput Digit Tech 2(6):471–482. https://doi.org/10.1049/iet-cdt:20070111

    Article  Google Scholar 

  57. Marcu M, Boncalo O, Weinstock JH, Leupers R (2016) Low-cost hardware infrastructure for runtime thread level energy accounting. In: ARCS 2016 - Architecture of Computing Systems, Nuremberg, Germany. https://doi.org/10.1007/978-3-319-30695-7_21

    Chapter  Google Scholar 

  58. Mehta H, Owens RM, Irwin MJ (1996) Instruction level power profiling. In: IEEE international conference on acoustics, speech, and signal processing conference proceedings, vol 6, pp 3326–3329. https://doi.org/10.1109/ICASSP.1996.550589

  59. Mentor Graphics Vista Flow (2017) Mentor graphics vista flow. https://www.mentor.com/esl/vista/flow/. Retrieved 26 March 2017

  60. Milojevic D, Montperrus L, Verkest D (2007) Power dissipation of the network-on-chip in a system-on-chip for MPEG-4 video encoding. In: 2007 IEEE Asian solid-state circuits conference, pp 392–395. https://doi.org/10.1109/ASSCC.2007.4425713

  61. Monchiero M, Palermo G, Silvano C, Villa O (2008) A modular approach to model heterogeneous MPSoC at cycle level. In: 11th EUROMICRO conference on digital system design architectures, methods and tools, pp 158–164. https://doi.org/10.1109/DSD.2008.84

  62. Moy M, Helmstetter C, Bouhadiba T, Maraninchi F (2016) Modeling power consumption and temperature in TLM models. Leibniz Trans Embed Syst 3:03:1–03:29. https://doi.org/10.4230/LITES-v003-i001-a003

  63. Nikolaidis S, Kavvadias N, Laopoulos T, Bisdounis L, Blionas S (2003) Instruction level energy modeling for pipelined processors. Springer, Berlin, pp 279–288. https://doi.org/10.1007/978-3-540-39762-5_34

    Google Scholar 

  64. Ost L, Guindani G, Moraes F, Indrusiak L, Määttä S (2011) Exploring NoC-based MPSoC design space with power estimation models. IEEE Des Test 28. https://doi.org/10.1109/MDT.2010.116

    Article  Google Scholar 

  65. Pasricha S, Park YH, Kurdahi FJ, Dutt N (2006) System-level power-performance trade-offs in bus matrix communication architecture synthesis. In: Proceedings of the 4th international conference on hardware/software codesign and system synthesis (CODES+ISSS). https://doi.org/10.1145/1176254.1176327

  66. Pasricha S, Park YH, Kurdahi FJ, Dutt N (2010) CAPPS: A framework for power and performance tradeoffs in bus-matrix-based on-chip communication architecture synthesis. IEEE Trans Very Large Scale Integr (VLSI) Syst 18(2):209–221. https://doi.org/10.1109/TVLSI.2008.2009304

    Article  Google Scholar 

  67. Pimentel A, Erbas C, Polstra S (2006) A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Trans Comput 55(2):99–112. https://doi.org/10.1109/TC.2006.16

    Article  Google Scholar 

  68. Piscitelli R, Pimentel AD (2012) A signature-based power model for MPSoC on FPGA. VLSI Design 2012. https://doi.org/10.1155/2012/196984

    Article  Google Scholar 

  69. Ptolemaeus C (ed) (2014) System design, modeling, and simulation using Ptolemy II. Ptolemy.org. http://ptolemy.org/books/Systems. Retrieved 24 Feb 2017

  70. Rethinagiri SK, Atitallah RB, Dekeyser JL (2011) A system level power consumption estimation for MPSoC. In: 2011 international symposium on system on chip. IEEE, Piscataway, pp 56–61. https://doi.org/10.1109/ISSOC.2011.6089692

    Chapter  Google Scholar 

  71. Rethinagiri SK, Palomar O, Ben Atitallah R, Niar S, Unsal O, Kestelman AC (2014) System-level power estimation tool for embedded processor based platforms. In: Proceedings of the 6th workshop on rapid simulation and performance evaluation: methods and tools, RAPIDO’14. ACM, New York, pp 5:1–5:8. https://doi.org/10.1145/2555486.2555491

  72. Rethinagiri SK, Palomar O, Moreno JA, Unsal O, Cristal A (2014) VPPET: virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms. In: 24th international workshop on power and timing modeling, optimization and simulation (PATMOS), pp 1–8. https://doi.org/10.1109/PATMOS.2014.6951910

  73. Rosa F, Ost L, Raupp T, Moraes F, Reis R (2014) Fast energy evaluation of embedded applications for many-core systems. In: 24th international workshop on power and timing modeling, optimization and simulation (PATMOS), pp 1–6. https://doi.org/10.1109/PATMOS.2014.6951893

  74. Russell JT, Jacome MF (1998) Software power estimation and optimization for high performance, 32-bit embedded processors. In: Proceedings international conference on computer design. VLSI in computers and processors, pp 328–333. https://doi.org/10.1109/ICCD.1998.727070

  75. Sami M, Sciuto D, Silvano C, Zaccaria V (2000) Power exploration for embedded VLIW architectures. In: IEEE/ACM international conference on computer aided design (ICCAD), pp 498–503. https://doi.org/10.1109/ICCAD.2000.896522

  76. Sami M, Sciuto D, Silvano C, Zaccaria V (2002) An instruction-level energy model for embedded VLIW architectures. IEEE Trans Comput-Aided Des Integr Circuits Syst 21(9):998–1010. https://doi.org/10.1109/TCAD.2002.801105

    Article  Google Scholar 

  77. Schürmans S (2018) Power estimation on electronic system level using linear power models. Dissertation, RWTH Aachen University, Aachen. https://doi.org/10.18154/RWTH-2018-223695

  78. Senn E, Julien N, Laurent J, Martin E (2002) Power consumption estimation of a C program for data-intensive applications, Springer, Berlin, pp 332–341. https://doi.org/10.1007/3-540-45716-X_33

    Google Scholar 

  79. Sinha A, Chandrakasan AP (2001) JouleTrack — a web based tool for software energy profiling. In: Proceedings of the 38th design automation conference (IEEE Cat. No.01CH37232), pp 220–225. https://doi.org/10.1145/378239.378467

  80. Steinke S, Knauer M, Wehmeyer L, Marwedel P (2001) An accurate and fine grain instruction-level energy model supporting software optimizations. In: Proceedings of international workshop on power and timing modeling, optimization and simulation (PATMOS), pp 3.2.1–3.2.10. http://www.semanticscholar.org/paper/An-Accurate-and-Fine-Grain-Instruction-Level-Energ-Steinke-Knauer/659d65312eb4d81b1b6b73408ed1753db1a2dcf5

  81. Streubühr M, Rosales R, Hasholzner R, Haubelt C, Teich J (2011) ESL power and performance estimation for heterogeneous MPSoCs using SystemC. In: Forum on specification and design languages, pp 1–8

    Google Scholar 

  82. Sultan S, Masud S (2009) Rapid software power estimation of embedded pipelined processor through instruction level power model. In: International symposium on performance evaluation of computer telecommunication systems, vol 41, pp 27–34

    Google Scholar 

  83. Synopsys Platform Architect MCO (2016) Synopsys platform architect MCO. https://www.synopsys.com/verification/prototyping/virtual-prototyping/platform-architect.html. Retrieved 22 Dec 2016

  84. SystemC (2014) SystemC 2.3. http://www.accellera.org/downloads/standards/systemc/files. Retrieved 20 Dec 2016

  85. Tiwari V, Lee MTC (1995) Power analysis of a 32-bit embedded microcontroller. In: Design Automation Conference, 1995. Proceedings of the ASP-DAC’95/CHDL’95/VLSI’95, IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal, pp 141–148. https://doi.org/10.1109/ASPDAC.1995.486215

  86. Tiwari V, Malik S, Wolfe A (1994) Power analysis of embedded software: a first step towards software power minimization. IEEE Trans Very Large Scale Integr Syst 2(4):437–445. https://doi.org/10.1109/ICCAD.1994.629825

    Article  Google Scholar 

  87. Tiwari V, Malik S, Wolfe A, Lee MTC (1996) Instruction level power analysis and optimization of software. In: Proceedings of 9th international conference on VLSI design, pp 326–328. https://doi.org/10.1109/ICVD.1996.489624

  88. Trabelsi C, Ben Atitallah R, Meftali S, Dekeyser JL, Jemai A (2011) A model-driven approach for hybrid power estimation in embedded systems design. EURASIP J Embed Syst https://doi.org/10.1155/2011/569031; http://link.springer.com/article/10.1155/2011/569031

    Article  Google Scholar 

  89. Varma A, Debes E, Kozintsev I, Klein P, Jacob B (2008) Accurate and fast system-level power modeling: an XScale-based case study. ACM Trans Embed Comput Syst 7(3):25:1–25:20. https://doi.org/10.1145/1347375.1347378

    Article  Google Scholar 

  90. Vece GB, Conti M (2009) Power estimation in embedded systems within a SystemC-based design context: the PKtool environment. In: Seventh workshop on intelligent solutions in embedded systems, pp 179–184

    Google Scholar 

  91. Veller Y, Matalon S (2010) Why you should optimize power at the ESL. http://go.mentor.com/cvtq. Retrieved Aug 13 2016

  92. Vijaykrishnan N, Kandemir M, Irwin MJ, Kim HS, Ye W (2000) Energy-driven integrated hardware-software optimizations using SimplePower. In: Proceedings of the 27th international symposium on computer architecture, 2000, pp 95–106. https://doi.org/10.1145/339647.339659

  93. Wang HS, Zhu X, Peh LS, Malik S (2002) Orion: a power-performance simulator for interconnection networks. In: Proceedings of 35th annual IEEE/ACM international symposium on microarchitecture, 2002. (MICRO-35), pp 294–305. https://doi.org/10.1109/MICRO.2002.1176258

  94. Xi J, Zhong P (2006) A transaction-level NoC simulation platform with architecture-level dynamic and leakage energy models. In: Proceedings of the 16th ACM great lakes symposium on VLSI, GLSVLSI’06. ACM, New York, pp 341–344. https://doi.org/10.1145/1127908.1127986

    Chapter  Google Scholar 

  95. Ye W, Vijaykrishnan N, Kandemir M, Irwin MJ (2000) The design and use of SimplePower: a cycle-accurate energy estimation tool. In: 37th design automation conference, DAC ’00. ACM, New York, pp 340–345. https://doi.org/10.1145/337292.337436

    Chapter  Google Scholar 

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Schuermans, S., Leupers, R. (2019). Related Work. In: Power Estimation on Electronic System Level using Linear Power Models. Springer, Cham. https://doi.org/10.1007/978-3-030-01875-7_2

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  • Print ISBN: 978-3-030-01874-0

  • Online ISBN: 978-3-030-01875-7

  • eBook Packages: EngineeringEngineering (R0)

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