Abstract
Real-time interaction with the outside world invariably is based on the abilityh of outside systems directly requesting service. The enhanced-range family’s interrupt architecture is the topic of this chapter.
The Interrupt system logic; including Control, Peripheral Enable, Flag and Priority registers are covered in conjunction with both Compatible and Priority modes. The design of interrupt handler routines for both single and multiple request events and transparency are also discussed.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
From the German Electrocardiogram; ECG in UK.
- 2.
It would of course make it easier just to ignore the phone!
- 3.
Alternatively, this could be the final cycle of a 2-cycle and/or 2-word instruction.
- 4.
See Program 7.1 in my Quintessential PIC ® Microcontroller for an example of the latter technique.
- 5.
Of course the delay subroutine can be interrupted, which will randomly slightly lengthen the delay. In time-critical situations interrupts should be disabled before calling the delay subroutine and re-enabled on return.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2010 Springer-Verlag London Limited
About this chapter
Cite this chapter
Katzen, S. (2010). Interrupt Handling. In: The Essential PIC18® Microcontroller. Computer Communications and Networks. Springer, London. https://doi.org/10.1007/978-1-84996-229-2_7
Download citation
DOI: https://doi.org/10.1007/978-1-84996-229-2_7
Publisher Name: Springer, London
Print ISBN: 978-1-84996-228-5
Online ISBN: 978-1-84996-229-2
eBook Packages: Computer ScienceComputer Science (R0)