Abstract
This paper looks at possible applications of Field Programmable Gate Arrays (FPGAs) within the safety critical domain. We examine the potential benefits these devices can offer, such as parallel computation and reconfiguration in the presence of failure and also the difficulties which these raise for certification. A possible safety argument supporting the use of basic reconfiguration facilities of a reprogrammable FPGA to remove Single Event Upsets (SEUs) is presented. We also demonstrate a technique which has the potential to be used to identify areas which are sensitive to SEUs in terms of safety effect, thus allowing optimisation of an FPGAs design and supporting our argument.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Ada HRG Group (1998) Guide for the use of the Ada programming language in High Integrity Systems, ISO/IEC
Bondhugula U, Devulapalli A et al (2006) Parallel FPGA-based All-Pairs Shortest-Paths in a Directed Graph. Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium. Rhodes Island, Greece, IEEE
Choi S, Govindu G et al (2003) Energy Efficient and Parameterized Designs for Fast Fourier Transform on FPGAs. IEEE International Conference on Acoustics, Speech and Signal Processing
Emmert JM, Stroud CE et al (2000) Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. IEEE Symposium on Field-Programmable Custom Computing Machines
Garvie M, Thompson A (2004) Scrubbing away transients and Jiggling around the permanent: Long survival of FPGA systems through evolutionary self-repair. Proc. 10th IEEE Intl. On- Line Testing Symposium
Glavinic V, Gros S et al (2000) Modelling and Simulation of a Hard Real-Time Processor. Journal of Computing and Information Technology 8:221-233
Graham P, Caffrey M et al (2003) Consequences and Categories of SRAM FPGA Configuration SEUs. Military and Aerospace Programmable Logic Devices International Conference
Hanchek F, Dutt S (1998) Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. IEEE Transactions on Computers 47:15-33
HISE Safety Critical Mailing List (2008) Are FPGAs Software? http://www.cs.york.ac.uk/hise/safety-critical-archive/2008/0138.html. Accessed 17 September 2008
IEC (2000) Functional safety of electrical/electronic/programmable electronic safety-related systems. IEC 61508
Isaac TA (2004) Firmware in Safety Critical Subsystems. International System Safety Conference, Providence, Rhode Island, USA
Kelly T (1998) Arguing Safety - A Systematic Approach to Managing Safety Cases. University of York. D. Phil.
Kowalski JE, Gromov KG et al (2005) High Altitude Subsonic Parachute Field Programmable Gate Array. http://klabs.org/mapld05/presento/154_kowalski_p.ppt. Accessed 17 September 2008
Kumar S, Paar C et al (2006) Breaking Ciphers with COPACOBANA - A Cost-Optimized Parallel Code Breaker. Cryptographic Hardware and Embedded Systems. Yokohama, Japan
Ministry of Defence (1999) Requirements for Safety Related Electronic Hardware in Defence Equipment (00-54) (now deprecated). Ministry of Defence, UK
Ministry of Defence (2007). Safety Management Requirements for Defence Systems, Part 1 Requirements (00-56). Ministry of Defence, UK
Morgan KS (2006) SEU-Induced Persistent Error Propagation in FPGAs. Department of Electrical and Computer Engineering, Brigham Young University. MSc.
Nallatech Ltd (2002) Improved Availability and Reduced Life Cycle Costs of Military Avionics Systems
Paige RF, Rose LM et al (2008) Automated Safety Analysis for Domain-Specific Languages. Workshop on Non-Functional System Properties in Domain Specific Modeling Languages
RTCA/EUROCAE (1992) Software Considerations in Airborne Systems and Equipment Certification, DO-178B/ED-12B, RTCA/EUROCAE
RTCA/EUROCAE (2000) Design Assurance Guidance for Airborne Electronic Hardware, DO- 254/ED-80, RTCA/EUROCAE
Stepney S (2003) CSP/FDR2 to Handel-C translation, University of York Report YCS-2003- 357:57
Sterpone L, Violante M (2005) A New Analytical Approach to Estimate the Effects of SEUs in TMR Architectures Implemented Through SRAM-Based FPGAs. IEEE Transactions on Nuclear Science 52:2217-2223
Wallace M (2005) Modular Architectural Representation and Analysis of Fault Propagation and Transformation. Proceedings of the Second International Workshop on Formal Foundations of Embedded Software and Component-based Software Architectures, Elsevier
Zarandi HR, Miremadi SG et al (2007) Fast SEU Detection and Correction in LUT Configuration Bits of SRAM FPGAs. 14th IEEE Reconfigurable Architecture Workshop, associated with IPDPS
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag London Limited
About this paper
Cite this paper
Bate, I., Conmy, P. (2009). Certification of FPGAs - Current Issues and Possible Solutions. In: Dale, C., Anderson, T. (eds) Safety-Critical Systems: Problems, Process and Practice. Springer, London. https://doi.org/10.1007/978-1-84882-349-5_9
Download citation
DOI: https://doi.org/10.1007/978-1-84882-349-5_9
Publisher Name: Springer, London
Print ISBN: 978-1-84882-348-8
Online ISBN: 978-1-84882-349-5
eBook Packages: Computer ScienceComputer Science (R0)