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Process Integration

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Abstract

Processing steps to integrate active and passive components in a CMOS base technology are discussed in this chapter. A basic description of unit processes is first presented. An overview of a baseline CMOS process is then given, followed by a discussion of process modules that are added to the baseline process to fabricate components for Mixed-Signal (MS) and Radio-Frequency (RF) CMOS, Analog CMOS, and Bipolar-CMOS-DMOS (BCD). Illustrative cross-sectional views of the numerous analog component constructions are provided.

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Author information

Authors and Affiliations

  1. PIYE, Cedar Park, TX, USA

    Badih El-Kareh

  2. Lou Hutter Consulting, Plano, TX, USA

    Lou N. Hutter

Authors
  1. Badih El-Kareh
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  2. Lou N. Hutter
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Corresponding author

Correspondence to Badih El-Kareh .

Problems

Problems

The temperature is 25 °C unless otherwise stated.

  1. 1.

    Describe a process with one polysilicon level and eight copper metal levels to fabricate the following components: LV CMOS, HV CMOS, isolated CMOS, DECMOS, LFC, NPN, and inductor. Assume existing metal levels are used for the inductor.

  2. 2.

    The four identical NMOS devices in the figure below must be isolated from substrate without changing their layout. Show a top view and cross-sectional view for how this can be done while minimizing the overall area consumed. Discuss your assumptions.

  3. 3.

    For an isolated native NMOSFET with a substrate concentration of 1015 cm−3 and a maximum drain voltage of 5.5 V

    1. (a)

      Show a top- and cross-sectional view.

    2. (b)

      Estimate the minimum channel length to avoid punch-through between source and drain.

    3. (c)

      Estimate the minimum distance between drain and underlying N-region required to avoid punch-through between the two regions.

Assume a step junction in both cases and N D = 5 × 1017 cm−3 in the deep N-region.

  1. 4.

    The figure below describes via etching to both plates of a MIM capacitor with oxide as the dielectric. Determine the minimum capacitor top-plate thickness under the following conditions: (a) IMD thickness = 1 μm. (b) Capacitor density = 1 fF/μm2. (c) A 10 % via over-etch of IMD is done. (d) The IMD to top-plate metal selectivity is 25:1. (e) The etched thickness of the top-plate metal must be <25 % of the original top-plate thickness.

  2. 5.

    Assume that the LDD of an NMOSFET with a rectangular polysilicon gate is implanted in a “4-way rotation” mode at an angle of 45° immediately after growing a 10-nm sidewall oxide, using resist as a mask. For a resist thickness of 800 nm, estimate the minimum space between resist edge and poly-edge required to avoid “shadowing” and ensure that the implanted dopants reach their maximum penetration and dose under the polysilicon. Assume that both the resist and poly-edges are vertical.

  3. 6.

    Consider an N+-polysilicon resistor placed on STI. A voltage of +5 V is applied to the resistor with respect to the underlying P-type substrate at ground.

    1. (a)

      Describe qualitatively how the resistor to substrate capacitance changes when a floating N-well is placed under the STI.

    2. (b)

      Estimate this change for an STI oxide thickness of 0.4 μm, a uniform N-well concentration of 1017 cm−3, and a uniform substrate concentration of N A = 1015 cm−3.

  4. 7.

    Estimate the minimum drawn NBL to NBL spacing required to achieve a 50 V punch-through voltage between two NBL regions shown in the figure below. Assume an epi thickness of 8 μm, a degenerately doped NBL with 1.7 μm lateral diffusion, N A = 1015 cm−3 in both epi and substrate, and planar NBL sidewalls (do not use cylindrical coordinates).

  5. 8.

    For a BCD epitaxy process using NBL, calculate the minimum epi thickness needed to achieve a 50 V avalanche breakdown voltage between P-body and NBL under the following conditions: P-body junction depth: x j = 1.5 μm; NBL up-diffusion into epi: 2 μm; P-epi concentration: N D = 1 × 1015 cm−3. Assume uniform P-body concentration N A = 5 × 1017 cm−3 and degenerately doped NBL.

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El-Kareh, B., Hutter, L.N. (2015). Process Integration. In: Silicon Analog Components. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2751-7_9

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  • DOI: https://doi.org/10.1007/978-1-4939-2751-7_9

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  • Online ISBN: 978-1-4939-2751-7

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