Integrated Circuit Design with Micro-relays

  • Hei Kam
  • Fred Chen
Chapter
Part of the Microsystems and Nanosystems book series (MICRONANO, volume 1)

Abstract

In the previous chapters, we discussed in detail many facets of micro-relay technology: from device fabrication and operation to scaling and energy implications. While the previous discussion aimed to demonstrate the viability of micro-relays as an underlying technology, the next two chapters will demonstrate how micro-relays can be integrated into the existing CMOS design infrastructure. As mentioned earlier, one of the unspoken criterion for a CMOS replacement technology is that it be compatible with the extensive existing infrastructure that has been built around CMOS technology [1]. This implied requirement is largely the reason behind choosing to explore the use of a four-terminal micro-relay first, since it shares functional similarities with an MOS transistor. In particular, we will show how micro-relays can implement many of the same functional circuits as used in CMOS at a lower energy cost while using the same simulation and design tool environments.

References

  1. 1.
    K. Bernstein, R.K. Cavin, W. Porod, A. Seabaugh, J. Welser, Device and architecture outlook for beyond CMOS switches. Proc. IEEE 98(12), 2169–2184 (2010)CrossRefGoogle Scholar
  2. 2.
    J.M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, 2nd edn. (Prentice Hall, Upper Saddle River, NJ, 2003)Google Scholar
  3. 3.
    P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th edn. (John Wiley & Sons, New York, 2009)Google Scholar
  4. 4.
    T. Gabara, S. Knauer, Digitally adjustable resistors in CMOS for high-performance applications. IEEE J. Solid-State Circuits 2(8), 1176–1185 (1992)CrossRefGoogle Scholar
  5. 5.
    M. Banu, Y. Tsividis, Fully integrated active RC filters in MOS technology, 1983 I.E. Int. Solid-State Circuits Conf. Dig. Tech. Pap., no. 6, pp. 244–245, 1983Google Scholar
  6. 6.
    L. Magnelli, F. Crupi, P. Corsonello, C. Pace, G. Iannaccone, S. Member, A 2.6 nW, 0.45 V temperature-compensated subthreshold CMOS voltage reference. IEEE J. Solid-State Circuits 46(2), 465–474 (2011)CrossRefGoogle Scholar
  7. 7.
    A. Tajalli, E. Brauer, Subthreshold source-coupled logic circuits for ultra-low-power applications. IEEE J. Solid-State Circuits 43(7), 1699–1710 (2008)CrossRefGoogle Scholar
  8. 8.
    L. Fay, V. Misra, R. Sarpeshkar, A micropower electrocardiogram amplifier. IEEE Trans. Biomed. Circuits Syst. 3(5), 312–20 (2009)CrossRefGoogle Scholar
  9. 9.
    O.H. Schmitt, A thermionic trigger. J. Sci. Instrum. 15, 24–26 (1938)CrossRefGoogle Scholar
  10. 10.
    R. Nathanael, V. Pott, H. Kam, J. Jeon, T.-J.K. Liu, 4-Terminal Relay Technology for Complementary Logic,” in IEDM, 2009, pp. 1–4Google Scholar
  11. 11.
    M. Spencer, F. Chen, C. Wang, R. Nathanael, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T.-J.K. Liu, D. Markovic, E. Alon, V. Stojanovic, Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications. IEEE J. Solid State Circuits 46(1), 308–320 (2011)CrossRefGoogle Scholar
  12. 12.
    M. Spencer, Design considerations for nano-electromechanical relay VLSI, Ph.D. Thesis, University of California, Berkeley, 2014Google Scholar
  13. 13.
    R. Holm, Electric Contacts (Springer-Verlag, Berlin, 1967)CrossRefGoogle Scholar
  14. 14.
    R. Maboudian, R.T. Howe, Critical review: adhesion in surface micromechanical structures. J. Vac. Sci. Technol. B Microelectron. Nanometer Struct. 15(1), 1–20 (1997)CrossRefGoogle Scholar
  15. 15.
    D. Maugis, Contact, Adhesion and Rupture of Elastic Surfaces (Springer Verlag, Berlin, 2000)CrossRefGoogle Scholar
  16. 16.
    D. Lee, V. Pott, H. Kam, R. Nathanael, T.-J.K. Liu, AFM characterization of adhesion force in micro-relays, in Micro Electro-Mechanical Systems (MEMS), 2010 I.E. 23rd International Conference, Jan. 2010, pp. 232–235Google Scholar
  17. 17.
    R. Nathanael, V. Pott, E. Alon, T.-J.K. Liu, Four-terminal-relay body-biasing schemes for complementary logic circuits. IEEE Electron. Dev. Lett. 31(8), 890–892 (2010)CrossRefGoogle Scholar
  18. 18.
    R. Nathanael, Nano-Electro-Mechanical (NEM) Relay Devices and Technology for Ultra-Low Energy Digital Integrated Circuits (University of California, Berkeley, 2012)Google Scholar
  19. 19.
    H. Fariborzi, F. Chen, Design and demonstration of micro-electro-mechanical relay multipliers, in IEEE Asian Solid-State Circuits Conference, 2011, pp. 6–9Google Scholar
  20. 20.
    I. Sutherland, B. Sproull, D. Harris, Logical Effort: Designing Fast CMOS Circuits, 1st edn. (Morgan Kaufmann, San Francisco, 1999)Google Scholar
  21. 21.
    Predictive Technology Model. (Online), http://ptm.asu.edu/
  22. 22.
    F. Chen, H. Kam, D. Markovic, T.-J.K. Liu, V. Stojanovic, E. Alon, Integrated circuit design with NEM relays, in 2008 IEEE/ACM International Conference on Computer-Aided Design, 2008, pp. 750–757Google Scholar
  23. 23.
    W. Keister, The logic of relay circuits. Trans. Am. Inst. Electr. Eng. 68(1), 571–576 (1949)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Hei Kam
    • 1
  • Fred Chen
    • 2
  1. 1.Intel CorporationHillsboroUSA
  2. 2.Lion Semiconductor, Inc.BerkeleyUSA

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