Integrated Circuit Design with Micro-relays

  • Hei Kam
  • Fred Chen
Part of the Microsystems and Nanosystems book series (MICRONANO, volume 1)


In the previous chapters, we discussed in detail many facets of micro-relay technology: from device fabrication and operation to scaling and energy implications. While the previous discussion aimed to demonstrate the viability of micro-relays as an underlying technology, the next two chapters will demonstrate how micro-relays can be integrated into the existing CMOS design infrastructure. As mentioned earlier, one of the unspoken criterion for a CMOS replacement technology is that it be compatible with the extensive existing infrastructure that has been built around CMOS technology [1]. This implied requirement is largely the reason behind choosing to explore the use of a four-terminal micro-relay first, since it shares functional similarities with an MOS transistor. In particular, we will show how micro-relays can implement many of the same functional circuits as used in CMOS at a lower energy cost while using the same simulation and design tool environments.


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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Hei Kam
    • 1
  • Fred Chen
    • 2
  1. 1.Intel CorporationHillsboroUSA
  2. 2.Lion Semiconductor, Inc.BerkeleyUSA

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