Abstract
This chapter begins with general overview of the relay energy-delay optimization, followed by a sensitivity-based energy-delay optimization methodology. We establish simple relay design guidelines and examine the implications of scaling relay devices using the proposed design methodology. We also show that in a manner highly analogous to MOSFET scaling, dimensional scaling can be applied to relays to improve device density, switching delay, and power consumption.
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Notes
- 1.
To establish the criteria to which the switching delay of a relay is dominated by mechanical delay, we first note that for the relay circuit as shown in Fig. 5.1, the electrical delay of the chain RC network can be estimated by the Elmore delay [2]:
$$ {t}_{RC}={\displaystyle \sum_{i=1}^N}\left({C}_i\times i\times {R}_{ON}\right) $$where R ON is the ON-state resistance of the relay. For the worst-case C i and R ON of 1fF and 10 kΩ, respectively, the Elmore delay is bounded by
$$ {t}_{RC}={\displaystyle {\sum}_{i=1}^N\left({C}_i\times i\times {R}_{ON}\right)}\le 10k\Omega \times 1fF\times \frac{N\left(N+1\right)}{2}\approx 5 ps\times {N}^2 $$As will be shown later in this chapter, the pull-in delay of a relay is in the nanosecond range; therefore, t RC is negligible so long as 5 ps × N 2 < < 1 ns or N < < 14.
- 2.
In a complex gate, not all the nodes (i.e., capacitances) switch with equal probability; therefore we can generalize the circuit to have an average activity.
- 3.
Since the optimal V dd is less than 2 × V pi, switching from high-to-low and low-to-high is asymmetric about V dd/2. Similarly as for CMOSFETs, the energy-delay optimal design for a relay is therefore not the same as a design optimized for static noise margin [14].
- 4.
Note that for a CMOS transistor driving a fixed capacitive load, one would also obtain similar optimal fixed-to-area-dependent capacitance ratio.
- 5.
Variations in C norm are much larger than those in V norm since V norm is close to 1 and therefore C norm—which is proportional to 1/(1 − V norm)—is a large number.
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Kam, H., Chen, F. (2015). Optimization and Scaling of Micro-relays for Ultralow-Power Digital Logic. In: Micro-Relay Technology for Energy-Efficient Integrated Circuits. Microsystems and Nanosystems, vol 1. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2128-7_5
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