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Part of the book series: Microsystems and Nanosystems ((MICRONANO,volume 1))

Abstract

One of the criteria often overlooked in the adoption of any technology is the cost viability of that technology at scale. In the case of the semiconductor industry, it was born out of the need for a cost-effective computing solution to replace unsustainable predecessors that used mechanical parts [1], magnetic relays [2], and vacuum tubes [3]. The industry’s more recent success can be traced back to the early 1970s when the industry began to transition from bipolar junction transistors (BJTs) to metal-oxide-semiconductor field-effect transistors (MOSFETs). Despite producing relatively slower transistors, MOSFET technology offered a lower power alternative that required a lower complexity and integration-friendly manufacturing process [4]. This transition to MOSFETs, and subsequently complementary metal-oxide-semiconductor (CMOS) technology, enabled the dramatic transistor scaling of the last several decades that has not only shrunk manufacturing cost but also yielded improvements in performance and functionality with each new technology generation. Combined with advancements in integrated circuit design, CMOS scaling has reduced the cost of data collection, computation, and communication such that it has fueled the adoption of electronics across an increasingly broad spectrum of applications [5].

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References

  1. A.G. Bromley, Charles Babbage’s analytical engine, 1838. IEEE Ann. Hist. Comput. 4(3), 196–217 (1982)

    Article  MathSciNet  MATH  Google Scholar 

  2. R. Rojas, Konrad Zuse’s legacy: the architecture of the Z1 and Z3. IEEE Ann. Hist. Comput. 19(2), 5–16 (1997)

    Article  Google Scholar 

  3. J. Kolodzey, CRAY-1 computer technology. IEEE Trans. Components Hybrids Manuf. Technol. 4(2), 181–186 (1981)

    Article  Google Scholar 

  4. C. Sah, Evolution of the MOS transistor-from conception to VLSI, Proc. IEEE, vol. 76, no. October 1988, pp. 1280–1326

    Google Scholar 

  5. W. Ballhaus, A. Pagella, C. Vogel, C. Wilmsmeier, Faster, Greener, Smarter—Reaching Beyond the Horizon in the World of Semiconductors (Price Waterhouse Coopers, Germany, 2012)

    Google Scholar 

  6. A. Sehgal, V. Perelman, Management of resource constrained devices in the internet of things, IEEE Communications, no. December 2012, pp. 144–149

    Google Scholar 

  7. A. Wang, B. Calhoun, A. Chandrakasan, Sub-threshold Design for ultra Low-power Systems (Springer, New York, 2006)

    Google Scholar 

  8. F. Chen, H. Kam, D. Markovic, T.-J. K. Liu, V. Stojanovic, E. Alon, Integrated circuit design with NEM relays, in 2008 IEEE/ACM International Conference on Computer-Aided Design, 2008, pp. 750–757

    Google Scholar 

  9. R. Nathanael, V. Pott, H. Kam, J. Jeon, T.-J. K. Liu, 4-terminal relay technology for complementary logic, in IEDM, 2009, pp. 1–4

    Google Scholar 

  10. Duracell, Technical Bulletin. (Online), http://www1.duracell.com/oem/primary/default.asp.

  11. S. Roundy, M. Strasser, P.K. Wright, Powering ambient intelligent networks, in Ambient Intelligence, ed. by J. Rabaey, W. Weber, E.H.L. Aarts (Springer, New York, 2005)

    Google Scholar 

  12. C. Links, Wireless sensor networks: maintenance-free or battery-free? RTC Mag 2, 18–21 (2009)

    Google Scholar 

  13. G. Moore, Cramming more components onto integrated circuits. Electronics 38(8), 114–117 (1965)

    Google Scholar 

  14. The International Technology Roadmap for Semiconductors (ITRS), 2012. (Online), http://www.itrs.net

  15. J.M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, 2nd edn. (Prentice Hall, Upper Saddle River, NJ, 2003)

    Google Scholar 

  16. R.H. Dennard, F.H. Gaensslen, H. Yu, V.L. Rideout, E. Bassous, A.R. LeBlanc, Design of ion-implanted MOSFET’s with very small physical dimensions. J. Solid-State Circuits SC-9(5), 256–268 (1974)

    Article  Google Scholar 

  17. E.J. Nowak, CMOS devices below 0.1 μm: how high will performance go? Int. Electron Devices Meet. IEDM Tech. Dig., 1997, pp. 215–218

    Google Scholar 

  18. Intel, Microprocessor Quick Reference Guide, 2008. (Online), http://www.intel.com/pressroom/kits/quickreffam.htm

  19. S. Borkar, Design challenges of technology scaling, Micro, IEEE, 1999, pp. 23–29

    Google Scholar 

  20. H. Kam, T.-J. K. Liu, E. Alon, M. Horowitz, Circuit-level requirements for MOSFET-replacement devices, 2008 I.E. Int. Electron Devices Meet, Dec 2008, pp. 1–1

    Google Scholar 

  21. B.H. Calhoun, A. Wang, A. Chandrakasan, Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE J. Solid-State Circuits 40(9), 1778–1786 (2005)

    Article  Google Scholar 

  22. S. Kim, H. Kam, C. Hu, and T. Liu, Germanium-source tunnel field effect transistors with record high ION/IOFF, Symposium on VLSI Technology, 2009, pp. 178–179

    Google Scholar 

  23. K.K. Bhuwalka, J. Schulze, I. Eisele, Performance enhancement of vertical tunnel field-effect transistor with SiGe in the δp+ layer. Jpn. J. Appl. Phys. 43(7A), 4073–4078 (2004)

    Article  Google Scholar 

  24. K. Gopalakrishnan, P.B. Griffin, J.D. Plummer, I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q, in Digest. International Electron Devices Meeting, 2002, pp. 289–292

    Google Scholar 

  25. W.Y. Choi, J.Y. Song, J.D. Lee, Y.J. Park, B.-G. Park, A novel biasing scheme for I-MOS (impact-ionization MOS) devices. IEEE Trans. Nanotechnol. 4, 322 (2005)

    Article  Google Scholar 

  26. S. Salahuddin, S. Datta, Use of negative capacitance to provide a sub-threshold slope lower than 60 mV/decade. Nanoletters 8(2), 405–410 (2008)

    Article  Google Scholar 

  27. S. Salahuddin, S. Datta, Can the subthreshold swing in a classical FET be lowered below 60 mV/decade?, in IEDM Tech. Dig., 2008, pp. 693–696

    Google Scholar 

  28. N. Abele, N. Fritschi, K. Boucart, F. Casset, P. Ancey, A.M. Ionescu, Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor, in IEDM Tech. Dig., 2005, pp. 1075–1077

    Google Scholar 

  29. H. Kam, D.T. Lee, R.T. Howe, T.-J. King, A new nano-electromechanical field effect transistor (NEMFET) design for low-power electronics, in IEDM Tech. Dig., 2005, pp. 463–466

    Google Scholar 

  30. K. Akarvardar, C. Eggimann, D. Tsamados, Y. Singh Chauhan, G.C. Wan, A.M. Ionescu, R.T. Howe, H.-S.P. Wong, Analytical modeling of the suspended-gate FET and design insights for low-power logic. IEEE Trans. Electron. Devices 55(1), 48–59 (2008)

    Article  Google Scholar 

  31. K. Akarvardar, D. Elata, R. Parsa, G.C. Wan, K. Yoo, J. Provine, P. Peumans, R.T. Howe, H.-S.P. Wong, Design considerations for complementary nanoelectromechanical logic gates, in IEDM Tech. Dig., 2007, pp. 299–302

    Google Scholar 

  32. H. Kam, V. Pott, R. Nathanael, J. Jeon, E. Alon, T.-J. King-Liu, Design and Reliability of a Micro-Relay Technology for Zero-Standby-Power Digital Logic Applications, in IEDM Tech. Dig., 2009, pp. 809–812

    Google Scholar 

  33. S.D. Senturia, Microsystem Design (Springer, Boston, 2000)

    Google Scholar 

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Kam, H., Chen, F. (2015). A New Era of Old Electronics. In: Micro-Relay Technology for Energy-Efficient Integrated Circuits. Microsystems and Nanosystems, vol 1. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2128-7_1

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  • DOI: https://doi.org/10.1007/978-1-4939-2128-7_1

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