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Hardware Approaches to Transactional Memory in Chip Multiprocessors

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Handbook on Data Centers

Abstract

Multicores are nowadays at the heart of almost every computational system, from the smartphone in our pocket, to the server-class machines in datacenters that provide us with a myriad of cloud services. With the advent of chip multiprocessors, the shift to mainstream parallel architectures is inevitable, and both programmers and architects are presented with immense opportunities and enormous challenges. Despite the fact that multiprocessor systems have existed for a long time, multi-threaded programming has not been much of a focus. Instead, multiprocessors were of interest only to the small community of high-performance computing (HPC), and so was parallel programming, which was mostly ignored by software vendors, and not widely investigated nor taught. As a matter of fact, most software development over time has been predicated on single-core hardware, and the collective knowledge of software developers across organizations has been based primarily on single processor platforms.

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References

  1. C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, and Sean Lie. Unbounded transactional memory. In Proceedings of the 11th Symposium on High-Performance Computer Architecture, pages 316–327, 2005.

    Google Scholar 

  2. Adria Armejach, Azam Seydi, Rubén Titos-Gil, Ibrahim Hur, Adrián Cristal, Osman Unsal, and Mateo Valero. Using a reconfigurable l1 data cache for efficient version management in hardware transactional memory. In Proceedings of the 20th International Conference on Parallel Architectures and Compilation Techniques, 2011.

    Google Scholar 

  3. Woongki Baek, Nathan Bronson, Christos Kozyrakis, and Kunle Olukotun. Making nested parallel transactions practical using lightweight hardware support. In Proceedings of the 24th International Conference of Supercomputing, pages 61–71, 2010.

    Google Scholar 

  4. Lee Baugh, Naveen Neelakantam, and Craig Zilles. Using hardware memory protection to build a high-performance, strongly atomic hybrid transactional memory. In Proceedings of the 35th International Symposium on Computer Architecture, pages 115–126. 2008.

    Google Scholar 

  5. Burton H. Bloom. Space/time trade-offs in hash coding with allowable errors. Communications of the ACM, 13:422–426, 1970.

    Google Scholar 

  6. Colin Blundell, E Christopher Lewis, and Milo Martin. Subtleties of transactional memory atomicity semantics. Computer Architecture Letters, 5(2), 2006.

    Google Scholar 

  7. Colin Blundell, E Christopher Lewis, and Milo M. K. Martin. Unrestricted transactional memory: Supporting i/o and system calls within transactions. Technical Report CIS-06-09, Department of Computer and Information Science, University of Pennsylvania, 2006.

    Google Scholar 

  8. Colin Blundell, Joe Devietti, E Christopher Lewis, and Milo Martin. Making the fast case common and the uncommon case simple in unbounded transactional memory. In Proceedings of the 34th International Symposium on Computer Architecture, pages 24–34, 2007.

    Google Scholar 

  9. Colin Blundell, Arun Raghavan, and Milo M.K. Martin. RETCON: transactional repair without replay. In Proceedings of the 37th International Symposium on Computer Architecture, pages 258–269, 2010.

    Google Scholar 

  10. Jayaram Bobba, Kevin E. Moore, Luke Yen, Haris Volos, Mark D. Hill, Michael M. Swift, and David A. Wood. Performance pathologies in hardware transactional memory. In Proceedings of the 34th International Symposium on Computer Architecture, pages 81–91, 2007.

    Google Scholar 

  11. Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael M. Swift, and David A. Wood. TokenTM: Efficient execution of large transactions with hardware transactional memory. In Proceedings of the 35th International Symposium on Computer Architecture, pages 81–91, 2008.

    Google Scholar 

  12. Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Austen McDonald, Nathan Bronson, Jared Casper, Christos Kozyrakis, and Kunle Olukotun. An effective hybrid transactional memory system with strong isolation guarantees. In Proceedings of the 34th International Symposium on Computer Architecture, pages 69–80, 2007.

    Google Scholar 

  13. Chi Cao Minh, JaeWoong Chung, Christos Kozyrakis, and Kunle Olukotun. STAMP: Stanford transactional applications for multi-processing. In Proceedings of the IEEE Intl. Symposium on Workload Characterization, pages 35–46, 2008.

    Google Scholar 

  14. Luis Ceze, James Tuck, Calin Cascaval, and Josep Torrellas. Bulk disambiguation of speculative threads in multiprocessors. In Proceedings of the 33rd International Symposium on Computer Architecture, pages 227–238, 2006.

    Google Scholar 

  15. Luis Ceze, James Tuck, Pablo Montesinos, and Josep Torrellas. BulkSC: bulk enforcement of sequential consistency. In Proceedings of the 34th International Symposium on Computer Architecture, pages 278–289, 2007.

    Google Scholar 

  16. Hassan Chafi, Jared Casper, Brian D. Carlstrom, Austen McDonald, Chi Cao Minh, Woongki Baek, Christos Kozyrakis, and Kunle Olukotun. A scalable, non-blocking approach to transactional memory. In Proceedings of the 13th Symposium on High-Performance Computer Architecture, pages 97–108, 2007.

    Google Scholar 

  17. Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, and Marc Tremblay. Rock: A high-performance Sparc CMT processor. IEEE Micro, 29(2):6–16, 2009.

    Google Scholar 

  18. Ben Chelf. Ensuring code quality in multi-threaded applications. http://www.coverity.com/1002library/pdf/coverity_multi-threaded_whitepaper.pdf.

  19. Weihaw Chuang, Satish Narayanasamy, Ganesh Venkatesh, Jack Sampson, Michael Van Biesbrouck, Gilles Pokam, Brad Calder, and Osvaldo Colavin. Unbounded page-based transactional memory. In Proceedings of the 12th International Symposium on Architectural Support for Programming Language and Operating Systems, pages 347–358, 2006.

    Google Scholar 

  20. JaeWoong Chung, Chi Cao Minh, Austen McDonald, Travis Skare, Hassan Chafi, Brian D. Carlstrom, Christos Kozyrakis, and Kunle Olukotun. Tradeoffs in transactional memory virtualization. In Proceedings of the 12th International Symposium on Architectural Support for Programming Language and Operating Systems, pages 371–381, 2006.

    Google Scholar 

  21. Jaewoong Chung, Luke Yen, Stephan Diestelhorst, Martin Pohlack, Michael Hohmuth, David Christie, and Dan Grossman. Asf: Amd64 extension for lock-free data structures and transactional memory. In Proceedings of the 43rd International Symposium on Microarchitecture, pages 39–50, 2010.

    Google Scholar 

  22. Cliff Click. Azul’s experiences with hardware transactional memory, 2009. http://sss.cs.purdue.edu/projects/tm/tmw2010/talks/Click-2010_TMW.pdf.

  23. Peter Damron, Alexandra Fedorova, Yossi Lev, Victor Luchangco, Mark Moir, and Daniel Nussbaum. Hybrid transactional memory. In Proceedings of the 12th International Symposium on Architectural Support for Programming Language and Operating Systems, pages 336–346, 2006.

    Google Scholar 

  24. James C. Dehnert, Brian K. Grant, John P. Banning, Richard Johnson, Thomas Kistler, Alexander Klaiber, and Jim Mattson. The transmeta code morphing software: using speculation, recovery, and adaptive retranslation to address real-life challenges. In Proceedings of the 1stInternational Symposium on Code Generation and Optimization (CGO).

    Google Scholar 

  25. Rajagopalan Desikan, Simha Sethumadhavan, Doug Burger, and Stephen W. Keckler. Scalable selective re-execution for edge architectures. In Proceedings of the 11th International Symposium on Architectural Support for Programming Language and Operating Systems, pages 120–132, 2004.

    Google Scholar 

  26. David Dice, Ori Shalev, and Nir Shavit. Transactional locking ii. In Proceedings of the 19th Intl. Symposium on Distributed Computing, 2006.

    Google Scholar 

  27. Ivan Dobos et al. IBM zEnterprise EC12 Technical Guide, February 2013. http://www.redbooks.ibm.com/redbooks/pdfs/sg248049.pdf.

  28. Aleksandar Dragojević, Maurice Herlihy, Yossi Lev, and Mark Moir. On the power of hardware transactional memory to simplify memory management. In Proceedings of the 30th International Symposium on Principles of Distributed Computing, pages 99–108, 2011.

    Google Scholar 

  29. J. Rubén Titos Gil, Manuel E. Acacio, and José M. García. Efficient eager management of conflicts for scalable hardware transactional memory. IEEE Transactions on Parallel and Distributed Systems, 24(1):59–71, 2013.

    Google Scholar 

  30. Tom Groenfeldt. Software programmers lag behind hardware developments, 2011. http://blogs.forbes.com/tomgroenfeldt/2011/04/21/software-programmers-lag-behind-hardware-developments/.

  31. Lance Hammond, Brian D. Carlstrom, Vicky Wong, Mike Chen, Christos Kozyrakis, and Kunle Olukotun. Transactional coherence and consistency: Simplifying parallel hardware and software. IEEE Micro, 24(6), 2004.

    Google Scholar 

  32. Lance Hammond, Vicky Wong, Mike Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, and Kunle Olukotun. Transactional memory coherence and consistency. In Proceedings of the 31st International Symposium on Computer Architecture, pages 102–113, 2004.

    Google Scholar 

  33. Ruud Haring, Martin Ohmacht, Thomas Fox, Michael Gschwind, David Satterfield, Krishnan Sugavanam, Paul Coteus, Philip Heidelberger, Matthias Blumrich, Robert Wisniewski, alan gara, George Chiu, Peter Boyle, Norman Chist, and Changhoan Kim. The ibm blue gene/q compute chip. IEEE Micro, 32(2):48–60, March 2012.

    Google Scholar 

  34. Tim Harris, James R. Larus, and Ravi Rajwar. Transactional Memory, 2nd Edition. Morgan & Claypool, 2010.

    Google Scholar 

  35. Maurice Herlihy, Victor Luchangco, Mark Moir, and III William N. Scherer. Software transactional memory for dynamic-sized data structures. In Proceedings of the 22nd Symposium on Principles of Distributed Computing, pages 92–101, 2003.

    Google Scholar 

  36. Maurice Herlihy and J. Eliot B. Moss. Transactional memory: Architectural support for lock-free data structures. In Proceedings of the 20th International Symposium on Computer Architecture, pages 289–300, 1993.

    Google Scholar 

  37. Owen S. Hofmann, Donald E. Porter, Christopher J. Rossbach, Hany E. Ramadan, and Emmett Witchel. Solving difficult HTM problems without difficult hardware. In TRANSACT '07: 2nd Workshop on Transactional Computing, 2007.

    Google Scholar 

  38. Owen S. Hofmann, Christopher J. Rossbach, and Emmett Witchel. Maximum benefit from a minimal HTM. In Proceedings of the 14th International Symposium on Architectural Support for Programming Language and Operating Systems, pages 145–156, 2009.

    Google Scholar 

  39. Jaehyuk Huh, Jichuan Chang, Doug Burger, and Gurindar S. Sohi. Coherence decoupling: making use of incoherence. In Proceedings of the 11th International Symposium on Architectural Support for Programming Language and Operating Systems, pages 97–106, 2004.

    Google Scholar 

  40. Christian Jacobi, Timothy Slegel, and Dan Greiner. Transactional memory architecture and implementation for IBM System z. In Proceedings of the 45th International Symposium on Microarchitecture, pages 25–36, 2012.

    Google Scholar 

  41. Syed Ali Raza Jafri, Mithuna Thottethodi, and T. N. Vijaykumar. LiteTM: Reducing transactional state overhead. In Proceedings of the 16th Symposium on High-Performance Computer Architecture, pages 1–12, 2010.

    Google Scholar 

  42. Behram Khan, Matthew Horsnell, Ian Rogers, Mikel Luján, Andrew Dinn, and Ian Watson. An object-aware hardware transactional memory. In Proceedings of the 10th International Conference on High Performance Computing and Communications, pages 93–102, 2008.

    Google Scholar 

  43. Sanjeev Kumar, Michael Chu, Christopher J. Hughes, Partha Kundu, and Anthony Nguyen. Hybrid transactional memory. In Proceedings of the 11th Symposium on Principles and Practice of Parallel Programming, pages 209–220, 2006.

    Google Scholar 

  44. Sean Lie. Hardware support for unbounded transactional memory. Master’s thesis, 2004. Massachusetts Institute of Technology.

    Google Scholar 

  45. Yi Liu, Xin Zhang, He Li, Mingxiu Li, and Depei Qian. Hardware transactional memory supporting I/O operations within transactions. In Proceedings of the 10th International Conference on High Performance Computing and Communications, pages 85–92, 2008.

    Google Scholar 

  46. Marc Lupon, Grigorios Magklis, and Antonio González. FASTM: A log-based hardware transactional memory with fast abort recovery. In Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques, pages 293–302, 2009.

    Google Scholar 

  47. Marc Lupon, Grigorios Magklis, and Antonio González. A dynamically adaptable hardware transactional memory. In Proceedings of the 43rd International Symposium on Microarchitecture, pages 27–38, 2010.

    Google Scholar 

  48. Virendra J. Marathe, William N. Scherer III, and Michael L. Scott. Adaptive software transactional memory. In Proceedings of the 19th Intl. Symposium on Distributed Computing, 2005.

    Google Scholar 

  49. Milo M.K. Martin. Token Coherence. PhD thesis, CS Dept., Univ. of Wisconsin-Madison, 2003.

    Google Scholar 

  50. Austen McDonald, JaeWoong Chung, D. Carlstrom Brian, Chi Cao Minh, Hassan Chafi, Christos Kozyrakis, and Kunle Olukotun. Architectural semantics for practical transactional memory. In Proceedings of the 33rd International Symposium on Computer Architecture, pages 53–65, 2006.

    Google Scholar 

  51. Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill, and David A. Wood. LogTM: Log-based transactional memory. In Proceedings of the 12th Symposium on High-Performance Computer Architecture, pages 254–265, 2006.

    Google Scholar 

  52. Michelle J. Moravan, Jayaram Bobba, Kevin E. Moore, Luke Yen, Mark D. Hill, Ben Liblit, Michael M. Swift, and David A. Wood. Supporting nested transactional memory in LogTM. In Proceedings of the 12th International Symposium on Architectural Support for Programming Language and Operating Systems, pages 359–370, 2006.

    Google Scholar 

  53. Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, and Per Stenström. Pi-tm: Pessimistic invalidation for scalable lazy hardware transactional memory. In Proceedings of the 18th Symposium on High-Performance Computer Architecture, pages 141–152, 2012.

    Google Scholar 

  54. Anurag Negi, M.M. Waliullah, and Per Stenstrom. LV*: A low complexity lazy versioning HTM infrastructure. In Proceedings of the Intl. Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2010), pages 231–240, 2010.

    Google Scholar 

  55. Yang Ni, Vijay S. Menon, Ali-Reza Adl-Tabatabai, Antony L. Hosking, Richard L. Hudson, J. Eliot B. Moss, Bratin Saha, and Tatiana Shpeisman. Open nesting in software transactional memory. In Proceedings 12th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming, pages 68–78, 2007.

    Google Scholar 

  56. Salil Pant and Gregory Byrd. Extending concurrency of transactional memory programs by using value prediction. In Proceedings of the 6th ACM conference on Computing Frontiers, pages 11–20, 2009.

    Google Scholar 

  57. Salil Pant and Gregory Byrd. Limited early value communication to improve performance of transactional memory. In Proceedings of the 23rd International Conference of Supercomputing, pages 421–429, 2009.

    Google Scholar 

  58. Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, and Rajeev Balasubramonian. Scalable and reliable communication for hardware transactional memory. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, pages 144–154, 2008.

    Google Scholar 

  59. Ricardo Quislant, Eladio Gutierrez, and Oscar Plata. Improving signatures by locality exploitation for transactional memory. In Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques, pages 303–312, 2009.

    Google Scholar 

  60. Ricardo Quislant, Eladio Gutierrez, and Oscar. Plata. Multiset signatures for transactional memory. In Proceedings of the 25th International Conference of Supercomputing, pages 43–52, 2011.

    Google Scholar 

  61. Ravi Rajwar and Martin Dixon. Intel transactional synchronization extensions, 2012. Intel Developer Forum (IDF2012).

    Google Scholar 

  62. Ravi Rajwar and James R. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In Proceedings of the 34th International Symposium on Microarchitecture, pages 294–305, 2001.

    Google Scholar 

  63. Ravi Rajwar and James R. Goodman. Transactional lock-free execution of lock-based programs. In Proceedings of the 10th International Symposium on Architectural Support for Programming Language and Operating Systems, pages 5–17, 2002.

    Google Scholar 

  64. Ravi Rajwar, Maurice Herlihy, and Konrad Lai. Virtualizing transactional memory. In Proceedings of the 32nd International Symposium on Computer Architecture, pages 494–505, 2005.

    Google Scholar 

  65. Hany E. Ramadan, Christopher J. Rossbach, Donald E. Porter, Owen S. Hofmann, Aditya Bhandari, and Emmett Witchel. MetaTM/TxLinux: transactional memory for an operating system. In Proceedings of the 34th International Symposium on Computer Architecture, pages 92–103, 2007.

    Google Scholar 

  66. Hany E. Ramadan, Christopher J. Rossbach, Owen S. Hofmann, and Emmett Witchel. Dependence-aware transactional memory. In Proceedings of the 41st International Symposium on Microarchitecture, pages 246–257, 2008.

    Google Scholar 

  67. Nicholas Riley and Craig Zilles. Hardware transactional memory support for lightweight dynamic language evolution. In Dynamic Language Symposium, 2006.

    Google Scholar 

  68. Christopher J. Rossbach, Hany E. Ramadan, Owen S. Hofmann, Donald E. Porter, Aditya Bhandari, and Emmett Witchel. TxLinux and MetaTM: transactional memory and the operating system. Communications of the ACM, 51:83–91, 2008.

    Google Scholar 

  69. Daniel Sanchez, Luke Yen, Mark D. Hill, and Karthikeyan Sankaralingam. Implementing signatures for transactional memory. In Proceedings of the 40th International Symposium on Microarchitecture, pages 123–133, 2007.

    Google Scholar 

  70. Sutirtha Sanyal, Adrián Cristal, Osman S. Unsal, Mateo Valero, and Sourav Roy. Dynamically filtering thread-local variables in lazy-lazy hardware transactional memory. In Proceedings of the 11th International Conference on High Performance Computing and Communications, pages 171–179, 2009.

    Google Scholar 

  71. Wang Shaogang, Dan Wu, Zhengbin Pang, and Xiaodong Yang. DTM: Decoupled hardware transactional memory to support unbounded transaction and operating system. In Proceedings of the 38th International Conference on Parallel Processing, pages 228–236, 2009.

    Google Scholar 

  72. Nir Shavit and Dan Touitou. Software transactional memory. In Proceedings of the 14th ACM Symposium on Principles of Distributed Computing, pages 204–213, 1995.

    Google Scholar 

  73. Arrvindh Shriraman and Sandhya Dwarkadas. Refereeing conflicts in hardware transactional memory. In Proceedings of the 23rd International Conference of Supercomputing, pages 136–146, 2009.

    Google Scholar 

  74. Arrvindh Shriraman, Virendra J. Marathe, Sandhya Dwarkadas, Michael L. Scott, David Eisenstat, Christopher Heriot, William N. Scherer III, and Michael F. Spear. Hardware acceleration of software transactional memory. In Workshop on Languages, Compilers, and Hardware Support for Transactional Computing (TRANSACT), 2006.

    Google Scholar 

  75. Arrvindh Shriraman, Sandhya Dwarkadas, and Michael L. Scott. Flexible decoupled transactional memory support. In Proceedings of the 35th International Symposium on Computer Architecture, pages 139–150, 2008.

    Google Scholar 

  76. Herb Sutter. The free lunch is over: A fundamental turn toward concurrency in software. 30(3), 2005.

    Google Scholar 

  77. Fuad Tabba, Cong Wang, James R. Goodman, and Mark Moir. NZTM: Nonblocking, zero-indirection transactional memory. In Workshop on Transactional Computing (TRANSACT), 2007.

    Google Scholar 

  78. Fuad Tabba, Andrew W. Hay, and James R. Goodman. Transactional conflict decoupling and value prediction. In Proceedings of the 25th International Conference of Supercomputing, pages 33–42, 2011.

    Google Scholar 

  79. Rubén Titos-Gil, Anurag Negi, Manuel E. Acacio, Jose M. Garcia, and Per Stenstrom. Zebra: A data-centric, hybrid-policy hardware transactional memory design. In Proceedings of the 25th International Conference of Supercomputing, pages 53–62, 2011.

    Google Scholar 

  80. Ruben Titos-Gil, Anurag Negi, Manuel E. Acacio, Jose M. Garcia, and Per Stenstrom. Eager beats lazy: Improving store management in eager hardware transactional memory. IEEE Transactions on Parallel and Distributed Systems, 99(PrePrints):1, 2012.

    Google Scholar 

  81. Sasa Tomic, Adrian Cristal, Osman Unsal, and Mateo Valero. Hardware transactional memory with operating system support, HTMOS. In Proceedings of the 13th European Conference on Parallel Processing (Euro-Par), pages 8–17, 2007.

    Google Scholar 

  82. Sasa Tomic, Cristian Perfumo, Chinmay Kulkarni, Adria Armejach, Adrián Cristal, Osman Unsal, Tim Harris, and Mateo Valero. EazyHTM: Eager-lazy hardware transactional memory. In Proceedings of the 42nd International Symposium on Microarchitecture, pages 145–155, 2009.

    Google Scholar 

  83. Hans Vandierendonck and Tom Mens. Averting the next software crisis. IEEE Computer, 44:88–90, 2011.

    Google Scholar 

  84. Haris Volos, Neelam Goyal, and Michael M. Swift. Pathological interaction of locks with transactional memory. In TRANSACT '08: 3rd Workshop on Transactional Computing, 2008.

    Google Scholar 

  85. M. M. Waliullah. Efficient partial roll-backing mechanism for transactional memory systems. Transactions on high-performance embedded architectures and compilers, 3:256–274, 2011.

    Google Scholar 

  86. M.M. Waliullah and Per Stenstrom. Reducing roll-back overhead in transactional memory systems by checkpointing conflicting accesses. In Proceedings of the 22nd International Parallel and Distributed Processing Symposium. 2008.

    Google Scholar 

  87. M. M. Waliullah and Per Stenstrom. Schemes for avoiding starvation in transactional memory systems. Concurrency and Computation: Practice and Experience, 21:859–873, 2009.

    Google Scholar 

  88. Steven C. Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Singh, and Anoop Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In Proceedings of the 22nd International Symposium on Computer Architecture, pages 24–36, 1995.

    Google Scholar 

  89. Luke Yen, Jayaram Bobba, Michael R. Marty, Kevin E. Moore, Haris Volos, Mark D. Hill, Michael M. Swift, and David A. Wood. LogTM-SE: Decoupling hardware transactional memory from caches. In Proceedings of the 13th Symposium on High-Performance Computer Architecture, pages 261–272, 2007.

    Google Scholar 

  90. Luke Yen, Stark C. Draper, and Mark D. Hill. Notary: Hardware techniques to enhance signatures. In Proceedings of the 41st International Symposium on Microarchitecture, pages 234–245, 2008.

    Google Scholar 

  91. Richard Yoo, Christopher Hughes, Konrad Lai, and Ravi Rajwar. Performance evaluation of intel transactional synchronization extensions for high performance computing. In Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), 2013.

    Google Scholar 

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Acknowledgements

This work was supported by the Spanish MINECO, as well as European Commission FEDER funds, under grant TIN2012-38341-C04-03.

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Authors and Affiliations

  1. Chalmers University of Technology, Gothenburg, Sweden

    J. Rubén Titos-Gil

  2. Universidad de Murcia, Murcia, Spain

    Manuel E. Acacio

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Correspondence to J. Rubén Titos-Gil .

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  1. Department of Electrical and Computer Engineering, North Dakota State University, Fargo, North Dakota, USA

    Samee U. Khan

  2. School of Information Technologies, The University of Sydney, Sydney, New South Wales, Australia

    Albert Y. Zomaya

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Titos-Gil, J., Acacio, M. (2015). Hardware Approaches to Transactional Memory in Chip Multiprocessors. In: Khan, S., Zomaya, A. (eds) Handbook on Data Centers. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2092-1_27

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