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Efficient Hardware-Supported Synchronization Mechanisms for Manycores

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Handbook on Data Centers

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Abstract

In this Chapter, we analyze and propose techniques to mitigate the problem of synchronization at server (manycore processor) level in datacenters. Particularly, we propose two different strategies that provide very efficient, scalable and lightweight hardware implementations for barriers and highly-contended locks. We implement our synchronization architectures using two different technologies. The first is a state-of-the-art full-custom technology, namely G-Lines, whilst the second is a costeffective mainstream industrial toolflow with an advanced 45 nm technology, or Standard technology.

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Notes

  1. 1.

    For simplicity, we assume that 8 cores per row can be materialized in G-Lines. Recall that this technology is limited to 7 cores per row and, for example, a 6×6-core server layout must be considered instead to span the simulated 2D-mesh 32-core system.

  2. 2.

    Note that, the results for the implementation that uses G-Lines are the same as those presented in Fig. 7.

  3. 3.

    TATAS-X means that one (X = 1) or two (X = 2) of the highly-contended locks have been implemented as ideal locks.

  4. 4.

    Note that all pairs of flags (one per lock) could be grouped in each core using one special lock register.

  5. 5.

    We use the terms links and wires interchangeably.

  6. 6.

    For simplicity, we assume that 8 cores per row can be materialized in G-Lines. Recall that this technology is limited to 7 cores per row and, for example, a 6×6-core server layout must be considered instead to span the simulated 2D-mesh 32-core system.

  7. 7.

    In this Chapter, highly-contended locks are those locks accessed by all threads simultaneously or very close in time.

  8. 8.

    Although Raytrace has 34 locks, we only include the results for the two most highly-contended locks (RAYTR-L1 and RAYTR-L2) and aggregate the rest (RAYTR-LR).

  9. 9.

    Note that, the results for the implementation that uses G-Lines are the same as those presented in Fig. 7.

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Acknowledgements

This work was supported by the Spanish MINECO, as well as European Commission FEDER funds, under grant TIN2012-38341-C04-03. This work was done while Juan Fernández was a member of the Computer Engineering Department of the University of Murcia.

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Authors and Affiliations

  1. Boston University, Boston, USA

    José L. Abellán

  2. Intel-Labs Barcelona, Barcelona, Spain

    Juan Fernández

  3. University of Murcia, Murcia, Spain

    Manuel E. Acacio

Authors
  1. José L. Abellán
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  2. Juan Fernández
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  3. Manuel E. Acacio
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Correspondence to José L. Abellán .

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Editors and Affiliations

  1. Department of Electrical and Computer Engineering, North Dakota State University, Fargo, North Dakota, USA

    Samee U. Khan

  2. School of Information Technologies, The University of Sydney, Sydney, New South Wales, Australia

    Albert Y. Zomaya

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Abellán, J., Fernández, J., Acacio, M. (2015). Efficient Hardware-Supported Synchronization Mechanisms for Manycores. In: Khan, S., Zomaya, A. (eds) Handbook on Data Centers. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2092-1_26

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