Abstract
CMOS chips are designed to function over the published tolerances of circuit components and over the range of specified environmental conditions. Electrical tests are defined to cover the range of operating conditions such as power supply voltage and temperature over which any chip may need to function. The data collected are analyzed to isolate factors influencing chip yield and performance. Understanding the various sources of variations and their characterization are therefore important components of electrical testing. Efforts are made to maximize yield by accommodating anticipated sources of variations in chip design and by minimizing their impact with continuous improvements in the manufacturing process.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Bansal A, Rao RM (2010) Variations: sources and characterization. In: Bhunia S, Mukhopadhyay S (eds) Low-power variation tolerant design in nanometer silicon, Chapter 1. Springer, Berlin
Orshansky M, Nassif S, Boning D (2007) Test structures for variability. In: Design for manufacturability and statistical design: a constructive approach. Springer, Berlin
Weste NH, Harris D (2010) CMOS VLSI design: a circuit and systems perspective, 4th edn. Addison-Wesley, Boston
Jaeger RC (2001) Introduction to microelectronic fabrication, vol 5, 2nd edn, Modular series on solid state devices. Prentice Hall, Upper Saddle River
Campbell SA (2007) Fabrication engineering at the micro and nanoscale. Oxford University Press, Oxford
Polonsky S, Bhushan M, Gattiker A, Weger A, Song P (2005) Photon emission microscopy of inter/intra chip device performance variations. Microelectron Reliab 45:1471–1475
Yazawa K, Kendig D, Christofferson J, Marconnet A, Shakouri A (2012) Fast transient and steady state thermal imaging of CMOS integrated circuit chips considering package thermal boundaries. In: IEEE 13th ITHERM conference, pp 1405–1411
Gattiker A (2008) Unravelling variability for process/product improvement. In: Proceedings of the international test conference, ITC’08, pp 1–9
Die per wafer calculator. http://mrhackerott.org/semiconductor-informatics/informatics/toolz/DPWCalculator/Input.html. Accessed 21 Jul 2014
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer Science+Business Media New York
About this chapter
Cite this chapter
Bhushan, M., Ketchen, M.B. (2015). Variability. In: CMOS Test and Evaluation. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-1349-7_6
Download citation
DOI: https://doi.org/10.1007/978-1-4939-1349-7_6
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4939-1348-0
Online ISBN: 978-1-4939-1349-7
eBook Packages: EngineeringEngineering (R0)