Abstract
It is often necessary to make a direct comparison among CMOS technologies offered by different foundries at a particular technology node, among different technology nodes, or between similar technologies on different substrates, such as bulk silicon and SOI. Such comparisons are used in guiding technology development, in benchmarking and selecting the most suitable CMOS manufacturing process or foundry for a given product, and in projecting CMOS product specifications in advance of full-scale design. Quantifiable and measurable metrics for key performance tracking parameters are defined at the device and circuit level. For a correct assessment, the integrity of compact models and EDA used tools for chip design needs to be validated over the full design window. The final verdict on the relative merits of different technologies, based on models or hardware data, can only be obtained with limited certainty.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
International technology roadmap for semiconductors: ITRS. http://www.itrs.net. Accessed 21 July 2014
Taur Y, Ning TH (2009) Fundamentals of modern VLSI devices, 2nd edn. Cambridge University Press, New York
Weste NH, Harris D (2010) CMOS VLSI design: a circuit and systems perspective, 4th edn. Addison-Wesley, Reading
Rabaey JM, Chandrakasan A, Nikolic B (2003) Digital integrated circuits, 2nd edn. Prentice Hall, Upper Saddle River
Moore GE (1965) Cramming more components onto integrated circuits. Electronics 38:114–117
Intel chips timeline. http://www.intel.com/content/www/us/en/history/history-intel-chips-timeline-poster.html. Accessed 21 July 2014
IBM System P. http://en.wikipedia.org/wiki/IBM_System_p. Accessed 21 July 2014
Ranade P, Ghani T, Kuhn K, Mistry K, Pae S (2005) High performance 35 nm LGATE CMOS transistors featuring NiSi metal gate (FUSI), uniaxial strained silicon channels and 1.2 nm gate oxide. In: Proceedings of the International electron device meeting IEDM 2005
Ho R, Mai KW, Horowitz MA (2001) The future of wires. Proc IEEE 89:490
Das KK, Walker SG, Bhushan M (2007) An integrated methodology for evaluating MOSFET and parasitic extraction models and variability. Proc IEEE 85:670–687
Shahidi GG (2002) SOI technology for the GHz era. IBM J Res Dev 46:121–131
Bhushan M, Ketchen MB (2011) Microelectronic test structures for CMOS technology. Springer, New York
Goo J-S, William RQ, Workman GO, Chen Q, Lee S, Nowak EJ (2008) Compact modeling and simulation of PD-SOI MOSFETs: current status and challenges. In: IEEE 2008 custom integrated circuits conference, CCIC, pp 265–272
Ketchen MB (2003) Competitive advantage of SOI from dynamic threshold shifts and reduced capacitance. In: Proceedings 2003 international symposium on VLSI technology, systems and applications, pp 129–132
Auth C, Cappelani A, Chun J-S, Dalis A, Davis A, et al (2008) 45 nm high-k + strained enhanced transistors. 2008 Symposium on VLSI technology, pp 128–129
Nikonov DE, Young IA (2013) Overview of beyond-CMOS devices and a uniform methodology for their benchmarking. Proc IEEE 101:2498–2533
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer Science+Business Media New York
About this chapter
Cite this chapter
Bhushan, M., Ketchen, M.B. (2015). CMOS Metrics and Model Evaluation. In: CMOS Test and Evaluation. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-1349-7_10
Download citation
DOI: https://doi.org/10.1007/978-1-4939-1349-7_10
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4939-1348-0
Online ISBN: 978-1-4939-1349-7
eBook Packages: EngineeringEngineering (R0)