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Overview of ILP Architectures

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Instruction Level Parallelism

Abstract

In this chapter we trace the history of computer architecture, focusing on the evolution of techniques for instruction-level parallelism. After briefly summarizing the early years of machine design, we focus on the development of out-of-order, pipelined, and multiple-issue processors. These are further divided into processors that do instruction scheduling entirely in hardware (e.g., superscalar machines) and those that expose the instruction scheduling to the compiler, particularly VLIW machines such as the Multiflow Trace, Cydra 5, and Itanium.

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Authors and Affiliations

  1. Department of Computer Science, Stanford University, Stanford, CA, USA

    Alex Aiken

  2. Department of Computer Science, University of California at Irvine, Irvine, CA, USA

    Utpal Banerjee

  3. MZ Inc., Palo Alto, USA

    Arun Kejariwal

  4. Center for Embedded Computer Systems, University of California at Irvine, Irvine, CA, USA

    Alexandru Nicolau

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Aiken, A., Banerjee, U., Kejariwal, A., Nicolau, A. (2016). Overview of ILP Architectures. In: Instruction Level Parallelism. Springer, Boston, MA. https://doi.org/10.1007/978-1-4899-7797-7_2

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