Advertisement

A Control View to Vision Architectures

  • Bertrand Zavidovique
  • Pierre Fiorini

Abstract

Trying to compare robot vision architectures to a mythic reference like the human system might appear somewhat ambitious and asks for precautions. First two major difficulties are outlined. Drawing analogies between systems from their outputs is risky: such a limit is illustrated through one formalizing example. So, better compare major features. But a zoology of vision machines is questioned when, aiming to a well informed architectural feature choice, a rapid presentation of trends in the field is proposed.

Then an approach closer to physics prompts to a classification from a control point of view: it reveals some duality between operations and communications.

A few visual operations are distinguished provided technology is not trailing behind. But a fair stress must be put on communication networks if properties likely suitable for comparison are to be found.

Keywords

Parallel Machine Interconnection Network Systolic Array Diffusion Kernel Memory Bank 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Y. Burnod, An Adaptative Neural Network: the Cerebral Cortex, Masson ed. (1988).Google Scholar
  2. 2.
    J. Dowling, The Vertebrate Retina: an Approchable Part of the Brain, Harvard University (1985).Google Scholar
  3. 3.
    C. Olivier, Stratégies d’acquisition, de traitement et de prise en compte d’informations en vue du contrôle d’un robot en environnement non structuré, Thèse Université Paris-sud, centre d’Orsay, F (1993).Google Scholar
  4. 4.
    D.A. Patterson and C.H. Sequin, RISC I: a Reduced Instruction Set VLSI Computer, 8th Int. Symposium on Computer Architecture IEEE (1983).Google Scholar
  5. 5.
    J.C. Heudin and C. Panetto, Les Architectures RISC, Dunod, Paris, F (1990).Google Scholar
  6. 6.
    A. Merigot and B. Zavidovique, Image Analysis on Massively Parallel Computers: an Architectural Point of View, International Journal of Pattern Recognition and Artificial Intelligence, Vol.6, No.2–3 (1992).Google Scholar
  7. 7.
    W.D. Hillis, The Connection Machine, MIT Press, Cambridge, MA (1985).Google Scholar
  8. 8.
    J.F. Palmer and G. Fox, The NCUBE Family of High-Performance Parallel Computer Systems, Third Conference on Hypercube Concurrent Computers and Applications, Vol.1, pp. 847–851 (1988).Google Scholar
  9. 9.
    M.J.B. Duff, Review of the CLIP Image Processing System, National Computer Conference, Anaheim, CA (1978).Google Scholar
  10. 10.
    S.H. Unger, A Computer Oriented Toward Spatial Problems, Proc. IRE, Vol.46, pp. 1744–1750 (1958).CrossRefGoogle Scholar
  11. 11.
    D.L. Slotnick, W.C. Borck, and R.C. McReynolds, The SOLOMON Computer, Proc. Western Joint Comp. Conf., pp. 87-107 (1962).Google Scholar
  12. 12.
    G.M. Barnes et al., The Illiac Computer, IEEE Trans. Comp., Vol.C.17, pp. 746–757 (1968).CrossRefGoogle Scholar
  13. 13.
    P.M. Flanders, A Unified Approach to a Class of Data Movements on an Array Processor, IEEE Trans. Comp., Vol.C31, No.9, pp. 809–819 (1982).CrossRefGoogle Scholar
  14. 14.
    K.E. Batcher, Design of a Massively Parallel Processor, IEEE Trans. Comp., Vol.29, pp. 836–840 (1980).CrossRefGoogle Scholar
  15. 15.
    J.L. Potter, Image Processing on the Massively Parallel Processor, IEEE Computer, pp. 62-67 (1983).Google Scholar
  16. 16.
    K.E. Batcher, Bit Serial Processing Systems, IEEE Trans. Comp., Vol.C51, No.5, pp. 377–384 (1982).CrossRefGoogle Scholar
  17. 17.
    R. Davis and D. Thomas, Geometric Arithmetic Parallel Processor; Systolic Array Chip Meets the Demand of Heavy Duty Processing, Electronic Design, pp. 207-218 (1984).Google Scholar
  18. 18.
    T.J. Fountain and M. Phil, Towards CLIP 6 an Extra Dimension, CAPAIDM (1981).Google Scholar
  19. 19.
    M.J.B. Duff, The Elements of Digital Picture Processing, in Real Time Parallel Computing, Onoe, Preston, and Rosenfeld eds., Plenum Press (1981).Google Scholar
  20. 20.
    M.J.B. Duff, Array Automata, Modern Cellular Automata, K. Preston and M.B J. Duff eds., Plenum Press, pp. 259-274 (1984).Google Scholar
  21. 21.
    K.P. Arvind, D.K. Robinson, and I.N. Parker, A VLSI Chip for real time image processing, IEEE Int. Symp. on Circuits and Systems, pp. 405-408 (1983).Google Scholar
  22. 22.
    K.P. Arvind and R.A. Ianucci, A Critique Of Multiprocessing Von Neumann Style Programming, Proc. of 10th annual Int. Conf. Comp. Arch. (1983).Google Scholar
  23. 23.
    M.J.B. Duff, Clip 4, a Large Scale Integrated Circuit Array Parallel Processor, Proc. 3rd Int. Conf. on Pattern Recognition, pp. 728-733 (1976).Google Scholar
  24. 24.
    C.D. Stamopoulos, Parallel Image Processing, IEEE Trans. Comp., Vol.C24, No.4, pp. 424–433 (1975).CrossRefGoogle Scholar
  25. 25.
    P.M. Flanders, Efficient High Speed Computing with the Distributed Array Processor, High Speed Computer and Algorithm Organization, Kuck et al. eds., Academic Press (1978).Google Scholar
  26. 26.
    P. Marks, Low Level Vision Using an Array Processor, Computer Graphics and Image Processing, Vol. 14, pp. 281–292(1980).CrossRefGoogle Scholar
  27. 27.
    T. Kondo et al., An LSI Adaptative Array Processor, IEEE Jour, of Solid State Circuits, Vol.SCI8, No.2, pp. 147–156(1983).CrossRefGoogle Scholar
  28. 28.
    M. Kidode, Image Processing Machines in Japan, IEEE Computer, Vol.16, No.1, pp. 68–80 (1983).CrossRefGoogle Scholar
  29. 29.
    The Connection Machine CM-5 Technical Summary, Thinking Machines Corp., Cambridge, MA (1991).Google Scholar
  30. 30.
    A.R. Hanson and E.M. Riseman, Segmentation of Natural Scenes, in Computer Vision System, Hanson-Riseman ed., Academic Press (1978).Google Scholar
  31. 31.
    S.L. Tanimoto, Regular Hierarchical Image and Processing Structures in Machine Vision, Computer Vision Systems, Hanson-Risemann ed., Academic Press (1978).Google Scholar
  32. 32.
    C.R. Dyer, A VLSI, Pyramid Machine for Hierarchical Image Processing, Proceeding PRIP, pp. 381-386 (1981).Google Scholar
  33. 33.
    J.M. Jolion, Analyse d’Image: Le Modèle Pyramidal, Traitement du Signal, Vol.7, No.1 (1990).Google Scholar
  34. 34.
    J.L. Bentley and H.T. Kung, A Tree Machine for Searching Problems, Conference on Parallel Processing, pp. 257-266(1979).Google Scholar
  35. 35.
    G. Son, A Highly Concurrent Tree Machine for Data Base Applications, Proc. Conf. on Parallel Processing, pp. 259-268 (1980).Google Scholar
  36. 36.
    V. Cantoni, S. Levialdi, M. Ferreti, and F. Maloberti, A Pyramid Project Using Integrated Technology, in Integrated Technology for Parallel Image Processing, S. Levialdi ed., Academic Press, London, UK, pp. 121–132 (1985).Google Scholar
  37. 37.
    D.H. Schaefner, D.H. Wilcox, and G.C. Harris, A Pyramid of MPP Processing Elements; Experiences and Plans, Hawaii Int. Conf. on System Sciences, pp. 178-184 (1985).Google Scholar
  38. 38.
    S.L. Tanimoto, A Hierarchical Cellular Logic for Pyramid Computers, Journal of Parallel and Distributed Processing, Vol.1, pp. 105–132 (1984).CrossRefGoogle Scholar
  39. 39.
    S.L. Tanimoto, T.J. Logocki, and R. Ling, A Prototype Pyramid Machine for Hierarchical Cellular Logic, Parallel Computer Vision, L. Uhr ed., Academic Press, New York, NY, pp. 43–83 (1987).Google Scholar
  40. 40.
    A. Merigot, B. Zavidovique, and F. Devos, SPHINX, A Pyramidal Approach to Parallel Image Processing, IEEE Workshop on Computer Architecture for Pattern Analysis and Image Database Management, pp. 107-111 (1985).Google Scholar
  41. 41.
    A. Merigot, Une Architecture Pyramidale d’un Multi-processeur Cellulaire pour le Traitement d’Images, Thèse à l’Univ. de Paris sud Orsay, F (1983).Google Scholar
  42. 42.
    A. Merigot, S. Bouaziz, F. Devos, J. Mehat, Ni Y, P. Clermont, and M. Eccher, Sphinx, un Processeur Pyramidal Massivement Parallèle pour la Vision Artificielle, 7ème Congrès Afcet Inria Paris (1989).Google Scholar
  43. 43.
    S.R. Sternberg, Biomedicai Image Processing, IEEE Computer, Vol.16, No.1, pp. 22–34 (1983).CrossRefGoogle Scholar
  44. 44.
    D.B. Gennery and B. Wilcox, A Pipelined Processor for Low Level Vision, IEEE (1985).Google Scholar
  45. 45.
    D.B. Gennery, T. Littwin, B. Wilcox, and B. Bon, Sensing and Perception Research for Space Telerobotics at JPL, CH2413-3/87/0000/0311$01.00 © IEEE (1987).Google Scholar
  46. 46.
    E.W. Kent, R. Lumia, and M.O. Shneier, PIPE, Tech. Report of the Sensory Interactive Robotics Group at NBS, Washington (1986).Google Scholar
  47. 47.
    H.T. Kung, Let’s Design Algorithms for VLSI, Proc. Caltech Conf. on VLSI 79, pp. 65-90 (1979).Google Scholar
  48. 48.
    H.T. Kung, The Structure of Parallel Algorithms, Advances in Computers, Vol.19, pp. 65–112 (1980).CrossRefGoogle Scholar
  49. 49.
    H.T. Kung, Special Purpose Devices for Signal and Image Processing, Int. Report CMU-CS-80-132 (1980).Google Scholar
  50. 50.
    H.T. Kung, Special Purpose Devices for Signal and Image Processing: an Opportunity in VLSI, Proc. SPIE, Real Time Signal Processing, Vol. 241, pp. 76–84 (1981).Google Scholar
  51. 51.
    H.T. Kung, Why Systolic Architectures?, IEEE Computer, Vol.15, No.1, pp. 37–46 (1982).CrossRefGoogle Scholar
  52. 52.
    P.M. Dew, A tutorial on Systolic Architectures for High Performance Processors, 2nd Internationnal Electronic Image Week, CESTA, Nice, F (1986).Google Scholar
  53. 53.
    U. Weiser and A. Davis, A Wavefront Notation Tool for VLSI Array Design, in VLSI Design and Computations, H.T. Kung ed., CS Press, Carnegie Mellon Univ, pp. 226–234 (1981).CrossRefGoogle Scholar
  54. 54.
    C.E. Leiserson and J.B. Saxe, Optimizing Synchronous Systems, Proc. 22nd Annual Symp. Foundations of Computer Science, IEEE Computer Society, pp. 23-36 (1981).Google Scholar
  55. 55.
    G.J. Li and B. Wah, Optimal Design of Systolic Arrays for Image Processing, Proc. Workshop on Computer Arch. for Pattern Analysis and Image Database (1983).Google Scholar
  56. 56.
    P. Quinton and Y. Robert, Algorithmes et Architectures Systoliques, Masson ed. (1989).Google Scholar
  57. 57.
    H.T. Kung, Systolic Algorithms for the CMU Warp Processor, Tech. Report CMU-CS-84-I58, Dept. of Comp. Sc., CMU Pittsbugh, PA (1984).Google Scholar
  58. 58.
    S. Borkar et al., iWARP: an Integrated Solution to High Speed Computing, Proc. of Supercomputing Cong., Orlando, FL, pp. 330-339 (1988).Google Scholar
  59. 59.
    M. Annaratone, E. Amoult, T.H. Gross, H.T. Kung et al., Warp Architecture and Implementation, 0884-7495/86/0000/0346$01.00 © IEEE (1986).Google Scholar
  60. 60.
    M. Annaratone, E. Amoult, T.H. Gross, H.T. Kung et al, Architecture of Warp, CH2409-1/87/0000/0264$01.00 © IEEE (1987).Google Scholar
  61. 61.
    M. Annaratone, E. Amoult, T.H. Gross, H.T. Kung et al., Applications Experience on Warp, National Computer Conference, pp. 149-159 (1987).Google Scholar
  62. 62.
    M. Annaratone et al., The WARP Computer: Architecture, Implementation and Performances, IEEE Trans. Computers 32, Vol.12, pp. 523–538 (1987).Google Scholar
  63. 63.
    C. Peterson, J. Sutton, and P. Wiley, iWARP: A 100 Mops LIW Microprocessor for Multicomputers, IEEE Micro, pp. 26-29 (1991).Google Scholar
  64. 64.
    J.B. Dennis, Dataflow Supercomputers, IEEE Computers, No.1 (1980).Google Scholar
  65. 65.
    S.Y. Kung, S.C. Lo, S.N. Jean, and J.N. Hwang, Wavefront Array Processors: Concept to Implementation, IEEE Computer 20(11), pp. 18–33 (1987).CrossRefGoogle Scholar
  66. 66.
    E.B. Davie, D.G. Higgins, and CD. Cawthorn, An Advanced Adaptative Antenna Test Bed Based on a Wavefront Array Processor System, Proc. Int. Workshop on Systolic arrays (1986).Google Scholar
  67. 67.
    B. Zavidovique, G. Quenot, A. Safir, C. Fortunel, F. Verdier, and J. Serot, Automatic Synthesis of Vision Automata, M. Bayoumi ed., VLSI Design Methodologies for DSP Architectures, Kluwer Academic Publishers (1993).Google Scholar
  68. 68.
    J. Backus, Can Programming be Liberated from the Von Neumann Style? A Functional Style and its Algebra of Programs, Comm. of ACM, Vol.21, No.8 (1978).Google Scholar
  69. 69.
    B. Zavidovique, V. Serfaty, and C. Fortunel, Mechanism to Capture and Communicate Image-Processing Expertise, Journal of IEEE Software, Vol.8, No.6, pp. 37–50 (1991).CrossRefGoogle Scholar
  70. 70.
    B. Zavidovique and P.L. Wendel, Computer Architecture for Machine Perception, Proc. CAMP’ 91, B. Zavidovique ed., Paris, F (1991).Google Scholar
  71. 71.
    G. Quenot and B. Zavidovique, A Data-Flow Processor for Real-Time Low-Level Image Processing, IEEE Custom Integrated Circuits Conference, San-Diego, CA (1991).Google Scholar
  72. 72.
    E. Allart and B. Zavidovique, Functional Image Processing through Implementation of Regular Data Flow Graphs, 21st Annual Asilomar Conf. on Signals, Systems on Computers Pacific Grove CA (1987).Google Scholar
  73. 73.
    E. Allart and B. Zavidovique, Image Processing VLSI Design through Functional Match between Algorithms and Architecture, IEEE Int. Symposium on Circuits and System, Espoo, Finland (1988).Google Scholar
  74. 74.
    E. Allart and B. Zavidovique, Functional Mapping for Low-level Image Processing Algorithms, IEEE Workshop on VLSI Signal Processing Systems, Monterey, USA (1988).Google Scholar
  75. 75.
    G. Quenot and B. Zavidovique, The ETCA Massively Parallel Data-Flow Computer for Real Time Image Processing, IEEE Int. Conf on Computer Design, Cambridge, MA (1992).Google Scholar
  76. 76.
    C.C. Weems and J.R. Burrill, The Image Understanding Architecture and its Programming Environment, in Parallel Architectures and Algorithms for Image Understanding, V.K. Prusanar-Kumar ed., Academic Press, Orlando, FL, pp. 525–562 (1991).Google Scholar
  77. 77.
    C.C. Weems et al., Image Understanding Architecture: Exploiting Potential Parallelism in Machine Vision, IEEE Computer, pp. 65-68 (1992).Google Scholar
  78. 78.
    The Connection Machine CM-2 Technical Summary, Thinking Machines Corporation (1990).Google Scholar
  79. 79.
    L. Uhr, Converging Pyramids of Arrays, Proc. CAPAIDM, pp. 31-34 (1981).Google Scholar
  80. 80.
    J.L. Basille, Structures parallèles et traitement d’image, Thèse d’état Univ. Paul Sabatier Toulouse (1985).Google Scholar
  81. 81.
    C. Williams and J. Rasure, (Khoros) A Visual Language for Image Processing, Proc. IEEE Computer Society Workshop on Visual Languages, Skokie, Illinois (1990).Google Scholar
  82. 82.
    S. Dacic, Conception et Exploitation Intuitive de Systèmes Informatiques Complexes, These de Doctorat, Univ de Paris XI, Orsay, F (1990).Google Scholar
  83. 83.
    J. Serot, G. Quenot, and B. Zavidovique, Functional Programming on a Data-Flow Architecture: Applications in Real Time Image Processing, Int. Journal of Machine Vision and Applications (1993).Google Scholar
  84. 84.
    M.J. Flynn, Some Computer Organizations and their Effectiveness, IEEE Trans. Computers C21(9), pp. 948–960 (1972).CrossRefGoogle Scholar
  85. 85.
    P. Clermont, Méthodes de Programmation de Machine Parallèle Pyramidale. Applications en Segmentation d’Image, Thèse Paris 7 (1990).Google Scholar
  86. 86.
    J.R. McGraw, The VAL Language: Description and Analysis, ACM Trans. Prog. Languages and Systems, No.4(1), pp. 44–82 (1982).CrossRefGoogle Scholar
  87. 87.
    J.R. McGraw et al., SISAL: Streams and Iterations in a Single Assignment Language, Language Ref. Manual, Vers 1.0, Lawrence Livermore Nat Lab, Livermore, CA (1983).Google Scholar
  88. 88.
    R.S. Nikhil, K. Pingali, and K.P. Arvind, Id Nouveau, CSG Tech. Memo 265, LCS, MIT (1986).Google Scholar
  89. 89.
    R.S. Nikhil, Id Reference Manual, Tech. Report CSG Memo 284, MIT lab CS, Cambridge, MA (1988).Google Scholar
  90. 90.
    W. W. Wadge and E. A. Ashcroft, Lucid, the Dataflow Programming Language, Academic Press, London, UK (1985).Google Scholar
  91. 91.
    L. Snyder, Introduction to the Configurable Highly Parallel Computer, IEEE Computer, Vol.15, No.1, pp. 47–64 (1982).CrossRefGoogle Scholar
  92. 92.
    I. Koren and G.B. Silberman, A Direct Mapping of Algorithms onto VLSI Processor Arrays Based on the Data Flow Approach, Proc. Int. Conf Parallel Processing, pp. 335-337 (1983).Google Scholar
  93. 93.
    I. Koren, B. Mendelson, I. Peled, and G.B. Silberman, A Data-Driven VLSI Array for Arbitrary Algorithms, IEEE Computer (1988).Google Scholar
  94. 94.
    M. Cornish et al., The TI Dataflow Architecture: the Power of Concurrency for Avionics, Proc. 3rd Int. Conf. Digital Avionics Systems, IEEE, Fort-Worth, TX, pp. 19-25 (1979).Google Scholar
  95. 95.
    R. Vedder and D. Finn, The Hughes Data Flow Multiprocessor: Architecture and Efficient Signal and Data Processing, Proc. 12th Symp. Computer Architecture, Boston, MA, pp. 324-332 (1985).Google Scholar
  96. 96.
    T. Jeffery, The μPD7281 Processor, Byte, pp. 237-246 (1985).Google Scholar
  97. 97.
    P. Kajfasz and B. Zavidovique, Hardware Implementation of Geometric Transforms of Images for Real Time Processing, Proc. 5th Int. Symp. Electronics and Information Sciences, Kobe, Japan (1986).Google Scholar
  98. 98.
    P. Kajfasz and B. Zavidovique, MORPHEE: A Multi-access Memory Unit for on the Fly Image Processing Applications, Proc. 2nd Int. Conf. Computers and Applications, Beijing, China (1987).Google Scholar
  99. 99.
    P. Missakian, M. Milgram, and B. Zavidovique, A Special Architecture for Dynamic Programming, ICCASSP/IEEE/ASI, Tokyo, Japan (1986).Google Scholar
  100. 100.
    G. Quenot, J. Mariani, J.J. Gangolf, and J.L. Gauvin, Dynamic Programming Processor for Speach Recognition, IEEE Journal of Solid State Circuits (1989).Google Scholar
  101. 101.
    M. Eccher and B. Zavidovique, C.O.L.I.S.E. Real-Time Région Détector Based on Algorithmic Decomposition, Twentieth Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA (1986).Google Scholar
  102. 102.
    M. Eccher, Architecture Parallèle Dédiée à l’Étude d’Automates de Vision en Temps Réel, Thèse de Doctorat, Univ de Franche-Comté (1992).Google Scholar
  103. 103.
    L. Palmier, Conception Fonctionnelle de Circuits Intégrés de Traitement d’Image, Thèse Université de Paris-Sud, Orsay, F (1985).Google Scholar
  104. 104.
    L. Palmier, C. Legrand, F. Devos, and B. Zavidovique, Le Circuit de Mise Sous Forme Locale, Colloque National de Conception de Circuits à la demande, Grenoble, F (1985).Google Scholar
  105. 105.
    L. Palmier, F. Devos, and B. Zavidovique, A Functional Operation Architecture For Image Processing, International Symposium On Circuits and Systems, Kyoto (1985).Google Scholar
  106. 106.
    L. Palmier, F. Devos, and B. Zavidovique, Les Circuits de Traitements du Signal: Une Approche Fonctionnelle, IASTED International Symposium, Paris, F (1985).Google Scholar
  107. 107.
    L. Palmier, M.P. Gayrard, and B. Zavidovique, VLSI Architecture of the “CURVE” Function for Image Processing, Computer Architecture for Pattern Analysis and Image Data Base Management, Miami Beach, FL (1985).Google Scholar
  108. 108.
    H. Waldburger, J.Y. Dufour, and B. Kruse, A Real Time System for Image Processing, Proc. of 1991 Workshop on Computer Arch. and Machine Perception, Paris, F (1991).Google Scholar
  109. 109.
    P.A. Ruetz and R.W. Brodersen, An Image-Recognition System Using Algorithmically Dedicated Integrated Circuits, Int. Journal of Machine Vision and Applications, No.1, pp. 3–22 (1988).CrossRefGoogle Scholar
  110. 110.
    J.C. Gittins, Multi-armed Bandit Allocation Indices, John Wiley and Sons, Chichester (1989).Google Scholar
  111. 111.
    B. Zavidovique, Contribution à la vision des robots, Thèse d’état Université de Besancon, F (1981).Google Scholar
  112. 112.
    B. Zavidovique and G. Stammon, Bilevel Processing of Multilevel Pictures, Pattern Recognition and Image Processing Conference, Dallas (1981).Google Scholar
  113. 113.
    T. Bernard, P. Nguyen, F. Devos, and B. Zavidovique, A 65x76 VLSI Retina for Rough Vision, Workshop on Comp. Arch. for Mach. Perception 91, Paris, F (1991).Google Scholar
  114. 114.
    B. Zavidovique and T. Bernard, Generic functions for on-chip vision, Invited Conference at IEEE Int. Conf. on Pattern Recognition, La Hague, NL (1992).Google Scholar
  115. 115.
    T. Bernard, Des Rétines Artificielles Intelligentes, Thèse Université Paris-Sud (1992).Google Scholar
  116. 116.
    T. Bernard, B. Zavidovique, and F. Devos, A Programmable Artificial Retina, IEEE Journal of Solid-state Circuits (1993).Google Scholar
  117. 117.
    S. Mallat, Review of Multifrequency Channel Decomposition of Images and Wavelets Models, IEEE Trans. on Acoustic Speech and Signal Processing (1989).Google Scholar
  118. 118.
    S. Mallat and S. Zhong, Signal Characterization from Multiscale Edges, Proc. of the 1990 IEEEI CPR (1990).Google Scholar
  119. 119.
    J. Shen and S. Castan, Edge Detection Based on Multiedge Models, Proc. of the SPIE’87, Cannes, F (1987).Google Scholar
  120. 120.
    C.A. Mead and M.A. Mahowald, A Silicon Model of Early Visual Processing, Neural Networks, Vol. 1, pp. 91–97 (1988).CrossRefGoogle Scholar
  121. 121.
    C.A. Mead, Analog VLSI and Neural Systems, Addison Wesley (1988).Google Scholar
  122. 122.
    T. Bernard, P. Garda, A. Reichart, B. Zavidovique, and F. Devos, Design of a Half-toning Integrated Circuit Based on Analog Quadratic Minimization by Non-linear Multistage Switched Capacitor Network, IEEE Int. Symp. on Circuits and Systems, Helsinki, Finland (1988).Google Scholar
  123. 123.
    T. Bernard, P. Garda, A. Reichart, B. Zavidovique, and F. Devos, A Family of Analog Neural Half-toning Techniques, 4th European Signal Processing Conference, Grenoble, F (1988).Google Scholar
  124. 124.
    T. Bernard, P. Garda, B. Zavidovique, and F. Devos, Ultra-small Implementation of a Neural Half-toning Technique, EURASIP Workshop on Neural Networks 90, Sesimbra, P (1990).Google Scholar
  125. 125.
    T. Bernard, From Sigma-Delta Modulation to Digital Half-toning of Images, IEEE ICASSP 1991, pp. 2805-2808, Toronto, Ontario, CDN (1991).Google Scholar
  126. 126.
    C.A. Mead, A Sensitive Electronic Photoreceptor, Chapell Hill Conf. on VLSI, Comp. Sc. Press, Rockville, Maryland, pp. 463–471 (1985).Google Scholar
  127. 127.
    C.A. Mead and M. Ismail ed., Analog VLSI Implementations of Neural Systems, Kluwer Academic Publishers, Norwell, MA (1989).Google Scholar
  128. 128.
    V. Hu and A. Kramer, P.K. Ko, EEPROMS as Analog Storage Devices for Neural Nets, Neural Networks, 1 Supll.I 385 (1988).Google Scholar
  129. 129.
    T. Bernard, Convolueur imageur électronique, French licence n°89, 16552, 14 December 1989.Google Scholar
  130. 130.
    C. Koch, J. Marroquin, and A. Yuille, Analog “Neuronal” Networks in Early Vision, Proc. Natl. Acad. Sci. USA83, pp. 4263–4267 (1986).PubMedCrossRefGoogle Scholar
  131. 131.
    J. Hutchinson, C. Koch, J. Luo, and C. Mead, Computing Motion Using Analog and Binary Resistive Networks, IEEE Computers, Vol.21, No.3, pp. 52–63 (1988).CrossRefGoogle Scholar
  132. 132.
    C. Koch, Seeing Chips: Analog VLSI Circuits for Computer Vision, Neural Compt., Vol. 1, pp. 184–200 (1989).CrossRefGoogle Scholar
  133. 133.
    C. Koch, J. Harris, T. Horiuchi, A. Hsu, and J. Luo, Real-time Computer Vision and Robotics Using Analog VLSI Circuits, Advances in Neural Information and Processing Systems, D. Touretsky ed., Morgan Kaufmann (1989).Google Scholar
  134. 134.
    C. Koch, Resistive Networks for Computer Vision: An Overview, An introduction to neural and electronic networks, S.F. Zornetzer, J.L. Davis, and C. Lau eds., Academic Press (1990).Google Scholar
  135. 135.
    C.M. Brown, Parallel Vision with the Butterfly Computer, Supercomputing, pp. 54-68 (1988).Google Scholar
  136. 136.
    The Connection Machine CM-5 Technical Summary, Thinking Machines Corporation, Cambridge, MA (1992).Google Scholar
  137. 137.
    C.E. Leiserson, Fat Trees: Universal Networks for Hardware-efficient Supercomp, IEEE Comp., pp. 892-901 (1985).Google Scholar
  138. 138.
    T.H. Szymanski and V.C Hamacher, On the Universality of Multipath Multistage Interconnection Networks, Journal of Parallel and Distributed Computing, Vol.7, pp. 541–569 (1989).CrossRefGoogle Scholar
  139. 139.
    G.F. Pfister and V.A. Norton, “Hot spot” contention and combining in multistage interconnection networks, IEEE Transactions on Computers, Vol.C34, No. 10 (1985).Google Scholar
  140. 140.
    F.T. Leighton, Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes, Morgan Kaufmann, San Mateo, CA (1992).Google Scholar
  141. 141.
    J.C Bermond and C. Peyrat, de Bruijn and Kautz networks: a competitor for the hypercube?, in Hypercube and Distributed Computers, J.P. Verjus and F. André eds., North Holland, pp. 279-294 (1989).Google Scholar
  142. 142.
    S. Cartier, Parallélisme de Contrôle et Fusions de Régions, 5èines Rencontres sur le Parallélisme, Brest, pp. 243-246 (1993).Google Scholar
  143. 143.
    W.J. Dally, Performance Analysis of k-ary n-cube Interconnection Networks, IEEE Trans Computers, Vol.39, pp. 775–785 (1990).CrossRefGoogle Scholar
  144. 144.
    W.J. Dally and CL. Seitz, Deadlock-free Message Routing in Multiprocessor Interconnection Networks, IEEE Trans Computers, Vol.36, pp. 547–553 (1987).CrossRefGoogle Scholar
  145. 145.
    L.M. Ni and P.K. McKinley, A Survey of Wormhole Routing Techniques in Direct Networks, IEEE Computer, Vol.26, pp. 62–76 (1993).CrossRefGoogle Scholar
  146. 146.
    J. Rothnie, Overview of the KSR1 Computer System, Kendall Square Research Report TR 9202001 (1992).Google Scholar
  147. 147.
    KSR1 Principles of Operations, Kendall Square Research (1992).Google Scholar
  148. 148.
    INTEL, Introduction to iWarp (1991).Google Scholar

Copyright information

© Springer Science+Business Media New York 1994

Authors and Affiliations

  • Bertrand Zavidovique
    • 1
  • Pierre Fiorini
    • 2
  1. 1.Institut d’Electronique FondamentaleUniversité Paris XI Centre d’OrsayParis OrsayFrance
  2. 2.Etablissement Technique Central de l’ArmementParisFrance

Personalised recommendations