Field-Programmable Gate Arrays

  • Changyi Gu


Now comes the “hard” part. The next three chapters are all about hardware, which covers a wide gamut of topics like FPGA, SOPC, LCD, etc. This chapter begins with an overview of the embedded hardware in general, followed by detailed discussions about FPGA and IP protection.


Clock Cycle Combinational Logic Gray Code FPGA Device Digital Logic 
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  1.  1.
    “Crossing the abyss: asynchronous signals in a synchronous world.” Mike Stein, Paradigm Works, EDN Magazine, July, 24, 2003Google Scholar
  2.  2.
    “Practical design for transferring signals between clock domains.” Michael Crews and Yong Yuenyongsgool, Philips Semiconductors, EDN Magazine, February, 20, 2003Google Scholar
  3.  3.
    Simulation and Synthesis Techniques for Asynchronous FIFO Design, Rev 1.2, Clifford E. Cummings, Sunburst Design, Inc., SNUG (Synopsys User Group Conference), San Jose, 2002Google Scholar
  4.  4.
    Verilog Digital Computer Design - Algorithms into Hardware. Mark Gordon Arnold, University of Wyoming, Prentice Hall PTR, 1999Google Scholar
  5.  5.
    Verilog HDL Synthesis - A Practical Primer. J. Bhasker, Bell Labs, Lucent Technologies, Star Galaxy Publishing, 1998Google Scholar
  6.  6.
    Verilog Digital System Design, Zainalabedin Navabi, Northeastern University, University of Tehran, McGraw-Hill, 1999Google Scholar
  7. 7.
    The Designer's Guide to VHDL, Third Edition., Peter J. Ashenden, Morgan Kaufmamn Publishers Inc., May 2008Google Scholar
  8.  8.
    Designing with FPGAs & CPLDs. Bob Zeidman, CMP Book, 2002Google Scholar
  9.  9.
    Verilog Designer's Library. Bob Zeidman, Prentice Hall PTR, 1999Google Scholar
  10. 10.
    SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling (Second Edition). Stuart Sutherland, Simon Davidmann, and Peter Flake, Springer Science+Business Media, October, 2010Google Scholar
  11. 11.
    SystemVerilog for Verification: A Guide to Learning the Testbench Language Features (Second Edition). Chris Spear, Springer Science+Business Media, November, 2010Google Scholar
  12. 12.
    “Microcontroller Oscillator Circuit Design Considerations.” Cathy Cox and Clay Merritt, Freescale Semiconductor, 2004Google Scholar
  13. 13.
    TCXO Application vs OCXO Application (Application Notes #803, REV 1), Dave Kenny, PLETRONICSGoogle Scholar
  14. 14.
    “Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever know which to use?”. Clifford E. Cummings and Don Mills, SNUG (Synopsys Users Group), San Jose, 2002Google Scholar
  15. 15.
    “Asynchronous & Synchronous Reset Design Techniques - Part Deux.” Clifford E. Cummings, Don Mills, Steve Golson, SNUG Boston 2003Google Scholar
  16. 16.
    Area-Time Complexity for VLSI, C. D. Thompson, Carnegie-Mellon University, CALTECH CONFERENCE ON VLSI, January, 1979Google Scholar
  17. 17.
    Some Area-Time Tradeoffs for VLSI, Richard P. Brent and Leslie M. Goldschlager, SIAM (Society for Industrial and Applied Mathematics) J. Comput., Vol. 11, No. 4, November, 1982Google Scholar
  18. 18.
    FPGA implementation of a DSP Core for Full Rate and Half Rate GSM Vocoders, Hamid Noori, Hossein Pedram, Ahmad Akbari, Shervin Sheidaei, The 12th International Conference on Microelectronics, Tehran, October 31 - November 2, 2000Google Scholar
  19. 19.
    LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) IP Cores User Guide, Altera Corp, December, 2014Google Scholar
  20. 20.
    The Art of PCB Reverse Engineering: Unraveling the Beauty of the Original Design, by Mr. Keng Tiong Ng, CreateSpace Independent Publishing Platform, February, 2015Google Scholar
  21. 21.
    ModelSim User’s Manual, Software Version 10.1c, Mentor Graphics Corporation, 2012Google Scholar
  22. 22.
    Thicket(TM) Family of Source Code Obfuscators, Sematic Designs, Incorporated (
  23. 23.
    HDL Code Obfuscation (Tcl Script), Aldec Inc. (
  24. 24.
    Quartus Prime Standard Edition Handbook Volume 1: Design and Synthesis, Altera Corporation, May 4, 2015Google Scholar
  25. 25.
    Synopsys FPGA Synthesis Synplify Pro for Microsemi Edition - User Guide, Synopsys, Inc. February, 2013Google Scholar
  26. 26.
    AN 593: Anti-Tamper Protection for Cyclone III LS Devices, Altera Corporation, October, 2009Google Scholar
  27. 27.
    MAX 10 FPGA Configuration User Guide, Altera Corporation, December 14, 2015Google Scholar
  28. 28.
    White Paper: Anti-Tamper Capabilities in FPGA Designs, Ver 1.0, Altera Corporation July, 2008Google Scholar
  29. 29.
    Omron D2FS Ultra Subminiature Anti-Tamper Switch, OMRON Corporation, 2013Google Scholar
  30. 30.
    AN528: Buried Capacitive Sensors for Tamper Protection, Rev 0.2, Silicon Laboratories Inc., July, 2013Google Scholar

Copyright information

© Changyi Gu 2016

Authors and Affiliations

  • Changyi Gu
    • 1
  1. 1.San DiegoUSA

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