Abstract
This paper proposes a new switching and connection structure for the fault-tolerant logic unit network, i.e., the k-out-of-n logic unit network. The k-out-of-n, k < n, unit group, called a block, is operated with k units being worked in the normal operation and the remaining (n-k) units being used as spares. The n switching parts in the block, instead of the traditional k ones, can also mask the faults in the switching part of the block. Under the proposed structure, an interconnection which theoretically minimizes the number of connections between the k-out-of-m and the k-out-of-n blocks (m = n > k) is demonstrated. The proposed structure is applied to the 16-bit processor and to the large-sized LSI chip. This gives the result that the processor with redundancy structure is implemented by 2.4 times hardware amount compared to the nonredundancy one, and the proposed structure can improve yield of the chip to any good value by increasing the number of blocks. This paper also proposes a new implementation method of automatic reconfiguration of this network using hardware permuter.
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References
K. Shimohigashi, “Defect-tolerant technique in semiconductor memory” (in Japanese), J. IECE Japan, 65, 9, 1000–1002 (Sept. 1982).
T. Mano, M. Wada, N. Ieda and M. Tanimoto, “A redundancy circuit for a fault-tolerant 256K MOS RAM”, IEEE J. Solid-State Circuit, SC-17, 4, 726–731 (Aug. 1982).
A. Avizienis, G.C. Gilley, F.P. Mathur, D.A. Rennels, J.A. Rohr and D.K. Rubin, “The STAR (self-testing and repairing) computer: An investigation of the theory and practice of fault-tolerant computer design”, IEEE Trans. Comput. C-20, 11, 1312–1321 (Nov. 1971).
M. Sami and R. Stefanelli, “Reconfigurable architectures for VLSI processing arrays”, Dig. of NCC, 565-577 (1983).
T. Kawada, Y. Takahashi, N. Tsuda, M. Waki and N. Hagiwara, “A pattern matching processor array with defect tolerance”, Dig. 33th ISSCC, WPM 8.4, 90-91 (Feb. 1986).
N. Tsuda, T. Satoh and T. Kawada, “A pipeline sorting chip”, Dig. 34th ISSCC, FAM 21.1, 270-271 (Feb. 1987).
E. Fujiwara and K. Matsuoka, “Fault-tolerant k-out-of-n logic unit networks” (in Japanese), Trans. IEICE Japan, J70-D, 9, 1791-1800, (Sept. 1987).
C. Berge, “Graphs and Hypergraphs”, North-Holland (1973).
M. Ichikawa, “Constant weight code generators”, CRC Tech. Rep. 82-7, Stanford University (June 1982).
K. Matsuoka and E. Fujiwara, “A hardware implementation of permuter”, Trans. IEICE Japan, J70-D, 10, 1995–1998 (Oct. 1987).
R. Sedgewick, “Permutation generation methods”, ACM Computing Surveys, 9, 2, 137–164 (1977).
G.G. Langdon, Jr., “An algorithm for generating permutations”, Communica tions of ACM, 10, 5, 298–299 (May 1967).
D.L. Peltzer, “Wafer-scale integration: The limits of VLSI?”, VLSI DESIGN, 43-47 (Sept. 1983).
D.R. Resnik, “Testability and maintenabillty with a new 6K gate array”, VLSI DESIGN, 34-38 (Mar./Apr. 1983).
W.E. Donath, “Placement and average interconnection lengths of computer logic”, IEEE Trans. Circuit and Systems, CAS-26, 4, 272–277 (Apr. 1979).
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© 1990 Springer Science+Business Media New York
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Fujiwara, E. (1990). Fault-Tolerant k-out-of-n Logic Unit Network with Minimum Interconnection. In: Stapper, C.H., Jain, V.K., Saucier, G. (eds) Defect and Fault Tolerance in VLSI Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-9957-6_9
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DOI: https://doi.org/10.1007/978-1-4757-9957-6_9
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