Fault-Tolerant k-out-of-n Logic Unit Network with Minimum Interconnection
This paper proposes a new switching and connection structure for the fault-tolerant logic unit network, i.e., the k-out-of-n logic unit network. The k-out-of-n, k < n, unit group, called a block, is operated with k units being worked in the normal operation and the remaining (n-k) units being used as spares. The n switching parts in the block, instead of the traditional k ones, can also mask the faults in the switching part of the block. Under the proposed structure, an interconnection which theoretically minimizes the number of connections between the k-out-of-m and the k-out-of-n blocks (m = n > k) is demonstrated. The proposed structure is applied to the 16-bit processor and to the large-sized LSI chip. This gives the result that the processor with redundancy structure is implemented by 2.4 times hardware amount compared to the nonredundancy one, and the proposed structure can improve yield of the chip to any good value by increasing the number of blocks. This paper also proposes a new implementation method of automatic reconfiguration of this network using hardware permuter.
KeywordsRedundancy Structure Triple Modular Redundancy Functional Logic Constant Weight Code Processor Organization
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