Fault-Tolerant k-out-of-n Logic Unit Network with Minimum Interconnection

  • E. Fujiwara


This paper proposes a new switching and connection structure for the fault-tolerant logic unit network, i.e., the k-out-of-n logic unit network. The k-out-of-n, k < n, unit group, called a block, is operated with k units being worked in the normal operation and the remaining (n-k) units being used as spares. The n switching parts in the block, instead of the traditional k ones, can also mask the faults in the switching part of the block. Under the proposed structure, an interconnection which theoretically minimizes the number of connections between the k-out-of-m and the k-out-of-n blocks (m = n > k) is demonstrated. The proposed structure is applied to the 16-bit processor and to the large-sized LSI chip. This gives the result that the processor with redundancy structure is implemented by 2.4 times hardware amount compared to the nonredundancy one, and the proposed structure can improve yield of the chip to any good value by increasing the number of blocks. This paper also proposes a new implementation method of automatic reconfiguration of this network using hardware permuter.


Redundancy Structure Triple Modular Redundancy Functional Logic Constant Weight Code Processor Organization 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    K. Shimohigashi, “Defect-tolerant technique in semiconductor memory” (in Japanese), J. IECE Japan, 65, 9, 1000–1002 (Sept. 1982).Google Scholar
  2. [2]
    T. Mano, M. Wada, N. Ieda and M. Tanimoto, “A redundancy circuit for a fault-tolerant 256K MOS RAM”, IEEE J. Solid-State Circuit, SC-17, 4, 726–731 (Aug. 1982).CrossRefGoogle Scholar
  3. [3]
    A. Avizienis, G.C. Gilley, F.P. Mathur, D.A. Rennels, J.A. Rohr and D.K. Rubin, “The STAR (self-testing and repairing) computer: An investigation of the theory and practice of fault-tolerant computer design”, IEEE Trans. Comput. C-20, 11, 1312–1321 (Nov. 1971).CrossRefGoogle Scholar
  4. [4]
    M. Sami and R. Stefanelli, “Reconfigurable architectures for VLSI processing arrays”, Dig. of NCC, 565-577 (1983).Google Scholar
  5. [5]
    T. Kawada, Y. Takahashi, N. Tsuda, M. Waki and N. Hagiwara, “A pattern matching processor array with defect tolerance”, Dig. 33th ISSCC, WPM 8.4, 90-91 (Feb. 1986).Google Scholar
  6. [6]
    N. Tsuda, T. Satoh and T. Kawada, “A pipeline sorting chip”, Dig. 34th ISSCC, FAM 21.1, 270-271 (Feb. 1987).Google Scholar
  7. [7]
    E. Fujiwara and K. Matsuoka, “Fault-tolerant k-out-of-n logic unit networks” (in Japanese), Trans. IEICE Japan, J70-D, 9, 1791-1800, (Sept. 1987).Google Scholar
  8. [8]
    C. Berge, “Graphs and Hypergraphs”, North-Holland (1973).Google Scholar
  9. [9]
    M. Ichikawa, “Constant weight code generators”, CRC Tech. Rep. 82-7, Stanford University (June 1982).Google Scholar
  10. [10]
    K. Matsuoka and E. Fujiwara, “A hardware implementation of permuter”, Trans. IEICE Japan, J70-D, 10, 1995–1998 (Oct. 1987).Google Scholar
  11. [11]
    R. Sedgewick, “Permutation generation methods”, ACM Computing Surveys, 9, 2, 137–164 (1977).MathSciNetzbMATHCrossRefGoogle Scholar
  12. [12]
    G.G. Langdon, Jr., “An algorithm for generating permutations”, Communica tions of ACM, 10, 5, 298–299 (May 1967).CrossRefGoogle Scholar
  13. [13]
    D.L. Peltzer, “Wafer-scale integration: The limits of VLSI?”, VLSI DESIGN, 43-47 (Sept. 1983).Google Scholar
  14. [14]
    D.R. Resnik, “Testability and maintenabillty with a new 6K gate array”, VLSI DESIGN, 34-38 (Mar./Apr. 1983).Google Scholar
  15. [15]
    W.E. Donath, “Placement and average interconnection lengths of computer logic”, IEEE Trans. Circuit and Systems, CAS-26, 4, 272–277 (Apr. 1979).CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • E. Fujiwara
    • 1
  1. 1.Dept. of Computer ScienceTokyo Institute of TechnologyOokayama, Meguro-Ku, TokyoJapan

Personalised recommendations