ASP Modules: WSI Building-Blocks for Cost-Effective Parallel Computing

  • R. M. Lea

Abstract

An important application class for Massively Parallel Processors (MPPs) includes real-time signal and data processing in real-world locations. In particular, computer vision systems (for aerospace, biomedical, automotive and general robotics environments), suggest typical examples.

Keywords

Data Communication Network Faulty Block Parallel Computing Technology Wafer Scale Integration Input Data Rate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    R.M. Lea, “The ASP: a cost-effective parallel microcomputer”, IEEE Micro, October 1988, pp. 10-29.Google Scholar
  2. [2]
    R.M. Lea, “ASP modules: cost-effective building blocks for real-time DSP systems”, Journal of VLSI Signal Processing, 1989, Vol. 1, pp. 61–76.Google Scholar
  3. [3]
    R.M. Lea, “A WSI image processor”, Wafer Scale Integration (ed. Swartzlander), Kluwer Academic Publishers, Chapter 5, 1988.Google Scholar
  4. [4]
    I.P. Jalowiecki, K.D. Warren and R.M. Lea, “WASP: A WSI Associative String Processor”, Proc. IEEE Int. Conf. on Wafer Scale Integration (eds. Swartzlander and Brewer), IEEE Computer Society Press, 1989, pp. 83-93.Google Scholar
  5. [5]
    R. Morgan and M. Soraya, “Future military avionics applications of wafer-scale technology”, Proc. IEEE Int. Conf. on Wafer Scale Integration (eds. Swartzlander and Brewer), IEEE Computer Society Press, 1989, pp. 1-12.Google Scholar
  6. [6]
    K.D. Warren, J.H. Reche, W.J. Jacobi and R.M. Lea, “A 3D HDI ASP: a cost-effective alternative to WSI signal processors”, Proc. IEEE Int. Conf. on Wafer Scale Integration (eds. Swartzlander and Brewer), IEEE Computer Society Press, 1989, pp. 267-276.Google Scholar
  7. [7]
    A. Krikelis and R.M. Lea, “Performance of the ASP on the DARPA architecture benchmark”, Proc. Frontiers 88, 2nd. Symp. on the Frontiers of Massively Parallel Computation, Fairfax Virginia, October 1988.Google Scholar
  8. [8]
    A. Krikelis, I. Kossioris and R.M. Lea, “Performance of the ASP on the DARPA architecture benchmark II”, Proc. DARPA Image Understanding Benchmark Workshop., Avon Connecticut, October 1988.Google Scholar
  9. [9]
    S. Lone, R.K. Bock, Y. Ermolin, W. Krischer, C. Ljuslin, K. Zografos, “Fine-grain parallel computer architectures in future triggers”, CERN report CERN-LAA RT/89-05, September 1989.Google Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • R. M. Lea
    • 1
  1. 1.Aspex Microsystems LtdBrunel UniversityUxbridge, MiddlesexUK

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