Yield Evaluation of a Soft-Configurable WSI Switch Network
A network of fault tolerant switches is used to implement a pipelined memory system, and some measures of its fault tolerance presented. Simulations directly from the circuit layout provide yield estimates for each circuit piece. Such simulations predict that random point defects will cause less than 1% of the 1266-transistor switches to fail. Yield estimates for each circuit piece are used as inputs to a yield model to evaluate the fault tolerance of the entire design.
KeywordsBalance Load Fault Tolerance Memory Block Switch Node Switch Path
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