Systematic Extraction of Critical Areas From IC Layouts

  • J. Pineda de Gyvez
  • J. A. G. Jess

Abstract

We present a new method to determine the sensitivity of layouts to spot defects. The models for fatal faults considered are unintended bridges and unintended cuts related to patterns in one layer. Our method is a deterministic geometrical construction of so-called “critical areas”. The classical prototype of this construction consists of three steps (in the case of bridges): (1)Extend all patterns by half of the defect size; (2)Compute all the mutual intersections of the extended patterns; (3)Compute the area of the union of all intersections. Applying the scanline principle and assuming N line segments of the original mask patterns leads to an algorithm with asymptotic complexity N 2 logN 2, a bound which is sharp in particular for large defect sizes. Our approach, based on the new concept of “susceptible sites” reduces this complexity to NlogN. Moreover only two scans are necessary to extract all “susceptible sites” which then are used to compute the “critical areas” for a whole set of points in a domain of defect sizes. Under a UNIX-C environment an implementation has been created which actually exhibits the theoretically predicted gain in speed. Complex layouts can be analysed under interactive operating conditions on standard workstations (in our case of the type Apollo 3000).

Keywords

Line Segment Critical Region Defect Size Critical Area Vertical Line Segment 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    C.H. Stapper, “Modeling of Integrated Circuit Defect Sensitivities”, IBM J. Res. Develop., Vol. 27, No. 6, November 1983, pp. 549–557.CrossRefGoogle Scholar
  2. 2.
    C.H. Stapper, “Modeling of defects in integrated circuit photolithographic patterns”, IBM J. Res. Develop., Vol. 28, No. 4, July 1984, pp. 461–475.CrossRefGoogle Scholar
  3. 3.
    A.V. Ferris-Prabhu, “Modeling the Critical Area in Yield Forecast”, IEEE Journal of Solid-State Circuits, Vol, SC-20, No. 4, August 1985, pp. 874–877.CrossRefGoogle Scholar
  4. 4.
    J.P. Shen, W. Maly, F.J. Ferguson, “Inductive Fault Analysis of MOS Integrated Circuits”, IEEE Design and Test of Computers, December 1985, pp. 13-26.Google Scholar
  5. 5.
    H. Walker, S. Director, “VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits”, IEEE Trans. Computer Aided Design, Vol. CAD-5, No. 4, October 1986, pp. 541–556.CrossRefGoogle Scholar
  6. 6.
    J. Pineda de Gyvez, J.A.G. Jess “On the Definition of Critical Areas for IC Photolithographic Spot Defects”. 1st European Test Conference, April 1989, pp. 152-158.Google Scholar
  7. 7.
    W. Maly, “Modeling of Lithography related yield losses for CAD of VLSI circuits”, IEEE Trans. Computer Aided Design, pp. 166-177, Vol. CAD-4, 1985.Google Scholar
  8. 8.
    I. Chen, A. Strojwas, “Realistic Yield Simulation for IC Structural Failures”, IEEE Trans. on Computer Aided Design, Vol. CAD-6, Nov. 1987, pp. 965–980.CrossRefGoogle Scholar
  9. 9.
    J.L. Bentley, T. Ottmann, “Algorithms for Reporting and Counting Geometric Intersections”, IEEE Trans. on Computing”, Vol. C-28, Sept. 1979.Google Scholar
  10. 10.
    F.P. Preparata, M.I. Shamos, “Computational Geometry: An Introduction”, Springer-Verlag, 1985.Google Scholar
  11. 11.
    W. Maly, J. Deszczka “Yield Estimation Model for VLSI Artwork Evaluation”, Electronic Letters, Vol 19. No. 6, March 1983, pp. 226–227.CrossRefGoogle Scholar
  12. 12.
    L.P.P.P van Ginneken, J.T.J. van Eijndhoven, J. Brouwers, “Doubly Folded Transistor Matrix Layout”, IEEE Int. Conference on Computer Aided Design”, Nov. 1988, pp. 134-137.Google Scholar
  13. 13.
    Sophie Gandemer, Bernard C. Trementin, Jean-Jacques Chariot “Critical Area and Critical Levels Calculation in I.C. Yield Modeling”, IEEE Trans. on Electron Devices, Vol. 35, No. 2, Feb. 1988, pp. 158–166.CrossRefGoogle Scholar
  14. 14.
    Jose Pineda de Gyvez. “LASER:A LAyout Sensitivity ExploreR. Report and User’s Manual”, Eindhoven University of Technology, EUT Report 89-E-216, March 1989.Google Scholar
  15. 15.
    Michael Rivier,“Random Yield Simulation Applied to Physical Circuit Design”, in Yield Modelling and Defect Tolerance in VLSI, editors Will Moore, Wojciech Maly, and Andrezej Strojwas, publisher Adam Hilger, Bristol and Philadelphia, 1987, pp. 111-120.Google Scholar
  16. 16.
    Wojciech Maly, Will Moore and Andrezej Strojwas, “Yield Loss Mechanisms and Defect Tolerance”, in Yield Modelling and Defect Tolerance in VLSI, editors Will Moore, Wojciech Maly, and Andrezej Strojwas, publisher Adam Hilger, Bristol and Philadelphia, 1987, pp. 3-30.Google Scholar
  17. 17.
    J.F.M. Theeuwen, M.R.C.M. Berkelaar, “Logic optimisation with technology and delay in mind”, Notes of the International workshop on logic synthesis, Research Triangle Park, North Carolina, May 12–15, 1987.Google Scholar
  18. 18.
    Steve Perry, Mike Mitchell, D. Pilling, “Yield Analysis Modeling”, 22nd Design Automation Conference, 1985, pp. 425-428.Google Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • J. Pineda de Gyvez
    • 1
  • J. A. G. Jess
    • 1
  1. 1.Dept. of Electrical EngineeringEindhoven University of TechnologyEindhovenThe Netherlands

Personalised recommendations